We are hiring! Are you passionate about Design for Testability (DFT) for complex SoCs and SoC chiplets in package? We need you! As a Senior DFT and Post-Silicon Lead, you will own the DFT implementation process, ensuring seamless integration with test and post-silicon validation teams. You will work with cutting-edge technology, collaborating closely with external IP providers, EDA vendors, and internal teams to deliver high-quality, high-performance SoCs or SiPs for mass production.
Key Responsibilities- Leadership & Team Management
- Lead and mentor the DFT and Post-Silicon engineering teams to drive innovation and efficiency.
- Provide technical direction, ensuring alignment with organizational goals.
- Foster a culture of continuous improvement and collaboration.
DFT Strategy & Execution- Define and implement DFT architectures to improve testability, debug capabilities, and manufacturability.
- Ensure proper insertion of DFT features such as scan chains, BIST (Built-In Self-Test), and JTAG interfaces.
- Optimize DFT methodologies to minimize test time, reduce cost, and improve quality/yield.
Test Development & Implementation- Develop and implement test plans and test strategies at silicon, package, and system levels.
- Define and develop automated test solutions for production and characterization.
- Ensure test coverage for all product development stages, from pre-silicon to mass production.
- Guarantee high yield on the final solution while considering chiplet complexities.
Cross-Functional Collaboration- Work closely with design, validation, packaging, and operations teams to ensure seamless integration of testing and manufacturability.
- Collaborate with product management to ensure alignment with customer requirements and timelines.
Process Improvement & Innovation- Continuously explore and implement new DFT methodologies and manufacturing processes.
- Lead initiatives for cost reduction, efficiency improvements, and quality enhancements in test and production.
