2024-06-04 16:07:49
ID
BE-1
Description
We're looking for individuals with more than 7 years of experience in synthesis, place & route flows and floorplaning and wireplanning. Experience in tape out. Experience in clock tree synthesis and/or custom clock trees is also very welcome. Experience in netlist power analysis tools (such as PrimeTime/PX) will also be key in these positions. You'll be working in floorplanning in a very advanced technology node, creating the synthesis and place & route flow, integrating several custom blocks and running the resulting p&r netlists though power analysis tools.
Requirements
- Bachelor's, Master's or PhD degree in computer science
- EDA Tools from Synopsys / Cadence / Mentor
- Scripting (tcl)
- +7 years of experience
- 2 tape outs at least
- Knowledge of physical design verification and sign-off methodologies, including timing closure and physical verification (DRC, LVS)
