In The Media
November 16, 2023
Semidynamics and Arteris Combine to Push AI and RISC-V Beyond

Arteris, Inc. and Semidynamics are collaborating to enhance the next generation of electronic components for artificial intelligence (AI), machine learning (ML) and high-performance computing (HPC) applications. The agreement sees the interoperability between Semidynamics' Atrevido and Avispado 64-bit RISC-V processor IP cores and Arteris’ Ncore cache coherent network-on-chip (NoC) system IP.

November 10, 2023
EPI announces the successful bring-up of the EPAC1.5 acceleration chip

The European Processor Initiative (EPI), a project with 30 partners from 10 European countries, with the goal of achieving Europe’s independence in HPC chip technologies and infrastructure, has announced the successful Manufacturing and Silicon Demonstration of its EPAC Accelerator chip version 1.5.

November 08, 2023
RISC-V Summit 2023: Embedded Editor Report

Also today, Semidynamics announced the launch of its first fully-coherent RISC-V Tensor unit that the company says will not only reduce latency, processor cycles and energy use, it will also, when married to the Vector regulators, solve the memory wall problem. Roger Espasa, CEO & Founder at Semidynamics Technology Services, said the full system is designed to be ideal for AI and machine learning embedded systems, thanks to the new Tensor unit, and the company’s customizable 64-bit cores, married to the vector regulators, Gazzillion data management software, and the unique architecture that brings all these units together in one piece.

November 07, 2023
Semidynamics Releases RISC-V Tensor Unit for AI

Collaboration with Signature IP yields multicore environment and CHI interconnect customizable for performance and optimizable for efficiency.
Customizability and scalability are among the most common requirements of artificial intelligence and machine learning applications. AI and ML regularly involve complex algorithms and require specialized hardware and software optimizations that promote high performance and efficiency.

November 07, 2023
[CN] Semidynamics and Arteris collaborate to accelerate AI RISC-V system-on-chip development

California, Campbell - November 2, 2023 - Arteris, Inc. (NASDAQ: AIP) is a leading system IP provider dedicated to accelerating the creation of System-on-Chips (SoCs). Semidynamics is a fully customizable high-bandwidth and high-performance RISC-V processor IP provider. Arteris and Semidynamics announced today the establishment of a partnership to accelerate electronic product innovation for Artificial Intelligence (AI), Machine Learning (ML), and High-Performance Computing (HPC) applications.
This partnership supports the interoperability between Semidynamics' Atrevido™ and Avispado™ 64-bit RISC-V processor IP cores and Arteris' Ncore high-speed Cache Coherent Network-on-Chip (NoC) system IP. This combined solution offers interoperability to expedite the development of AI/ML and HPC designs.

November 07, 2023
[CN] Semidynamics and Arteris collaborate to accelerate AI RISC-V System-on-Chip development.

Arteris, Inc. (NASDAQ: AIP) is a leading system IP provider dedicated to accelerating the creation of System-on-Chips (SoCs). Semidynamics is a fully customizable high-bandwidth and high-performance RISC-V processor IP provider. Arteris and Semidynamics announced today the establishment of a partnership to accelerate electronic product innovation for Artificial Intelligence (AI), Machine Learning (ML), and High-Performance Computing (HPC) applications.

November 06, 2023
Arteris and Semidynamics hook up to accelerate SoC design

Arteris, a provider of system IP which accelerates SoC design, and Semidynamics, a provider of fully customisable high bandwidth and high-performance RISC-V processor IP, have partnered to accelerate electronic product innovation for AI, ML and HPC applications.
The partnership supports the interoperability between Semidynamics’ Atrevido and Avispado 64-bit RISC-V processor IP cores and Arteris’ Ncore cache coherent network-on-chip (NoC) system IP.

October 27, 2023
RISC-V Tensor Unit Enables Energy Efficient AI Processing

Intended for use in ultra-fast artificial intelligence (AI) implementations, a RISC-V Tensor Unit has just been introduced by Semidynamics.
Relying on the company’s configurable 64-bit cores, this presents customers with hardware that is highly optimised to meet the requirements of matrix multiplication workloads. The result is a solution that can handle intense computation demands while still keeping the power budget involved to a minimum. 

October 27, 2023
[FN] RISC-V jauhamaan tekoälyn suuria kielimalleja

LLM- eli suurten kielimallien merkitys näkyy nyt kaikkialla. Nämä mallit kuten LLaMa-2 tai ChatGPT koostuvat miljardeista parametreista ja vaativat suuren laskentatehon. Tähän useiden biljoonien toimintojen laskentakykyyn pitää pystyä alhaisella energiankulutuksella. Enpanjalaisen Semidynamicsin mukaan RISC-V on laskentaan sopiva alusta.

October 25, 2023
[FR] Semidynamics et SignatureIP veulent faciliter la conception de puces RISC-V multicœurs grâce à l’intégration d’un "réseau sur puce"

Il existe aujourd’hui une demande croissante pour des puces toujours plus puissantes pour des applications avancées telles que l'intelligence artificielle (IA) et l’apprentissage automatique (ML), technologies qui nécessitent souvent plusieurs cœurs sur une seule puce. Pour faciliter cette évolution en particulier pour des puces RISC-V multicœurs, les sociétés Semidynamics et SignatureIP se sont associées pour intégrer leurs IP respectives afin de fournir un environnement multicœur RISC-V entièrement testé, ainsi qu’une interconnexion CHI (Coherent Hub Interface) pour la conceptions de puces complexes.

October 24, 2023
Semidynamics launches first fully-coherent RISC-V Tensor unit to supercharge AI applications

Optimised for its 64-bit fully customisable RISC-V cores.
Semidynamics has just announced a RISC-V Tensor Unit that is designed for ultra-fast AI solutions and is based on its fully customisable 64-bit cores.

October 24, 2023
Semidynamics launches first fully-coherent RISC-V Tensor unit

Semidynamics has announced a RISC-V Tensor Unit that is designed for ultra-fast AI solutions and is based on its fully customisable 64-bit cores.
State-of-the-art Machine Learning models, such as LLaMa-2 or ChatGPT, consist of billions of parameters and require a large computation power in the order of several trillions of operations per second. Consequently, delivering such massive performance while keeping energy consumption low is a significant challenge for hardware design.

October 24, 2023
[SE] Spansk Risc V-baserad AI-IP

Semidynamics i Barcelona lanserar en neuronkärna baserad på den fria arkitekturen Risc V. Samtidigt presenterar företaget en processorarkitektur för artificiella neuronnät.
Neuronkärnan (omväxlande kallad NPU och TPU, tensorenhet) är inte Semidynamics första Risc V-baserade kärna. Företaget har sedan tidigare en VPU (Vector Processing Unit) och två 64-bitars CPU:er – allt baserat på Risc V.

October 10, 2023
Semidynamics and Signature IP Expand Multi-Core RISC-V and CHI Options

Two relatively new players in the CPU world, Semidynamics and Signature IP, have announced multi-core RISC-V and CHI interconnect IP for compute-intensive applications like AI/ML.
As some experts predict the end of Moore’s law, the artificial intelligence and machine learning (AL/ML) industry needs to find ways to greatly increase computing power density and efficiency. Such gains call for monolithic multi-core and chiplet architectures and improved interconnects.

October 08, 2023
Fully-Tested Multi-Core Environment for Development of RISC-V Based Chips

Semidynamics has collaborated with Californian start-up SignatureIP on the creation of a fully-tested interoperable RISC-V, multi-core environment plus CHI interconnect.
It draws on the companies’ respective customisable 64-bit RISC-V processing IP and Coherent NoC IP elements. Consequently, this will be able to help speed-up and de-risk next generation chip design projects - so that demanding artificial intelligence (AI) workloads can be dealt with. SignatureIP’s Coherent NoC IP delivers strong performance alongside inherent scalability. It supports a transport layer for chiplet communication. Semidynamics’ multi-core architecture provides an easily configurable platform for designers to work with.  

October 04, 2023
RISC-V Environment and CHI Interconnect for AI and ML Applications

Semidynamics and SignatureIP are collaborating to incorporate respected technologies for a completely assessed multi-core RISC-V environment and CHI interconnect for innovations in chip development for AI and ML applications. The solution utilizes SignatureIP’s Coherent NoC, designed to be scalable with the inclusion of a transport layer for chiplet communication and acts as an ordered file system with support for home-node resource group.

October 03, 2023
Partnership creates RISC-V multi-core environment

There is an ever-increasing demand for more powerful chip designs for advanced applications, such as AI and ML, that require many cores on one chip and RISC-V technology is particularly suitable for such requirements.
To facilitate this, Semidynamics and SignatureIP have partnered to integrate their respective IPs to provide a fully-tested RISC-V, multi-core environment and CHI interconnect for the development of state-of-the-art chip designs.

October 03, 2023
SemiDynamics teams for multicore RISC-V chiplet boost

Semidynamics in Spain has teamed up with SignatureIP in the US to combine multi-core RISC-V IP with CHI interconnect for the development of the latest chiplet AI chips.
SignatureIP’s Coherent network on chip (NoC) IP is designed for chiplet designs and supports a transport layer for chiplet communication using ARM’s Coherent Hub Interface (CHI) interconnect standard.

July 20, 2023
Semidynamics announces fully customisable, 4-way, Atrevido 423 RISC-V core for big data applications

Semidynamics, the only provider of fully customisable RISC-V processor IP, has launched the next member of its Atrevido family of 64-bit cores. The Atrevido 423 has a wider, 4-way pipeline, allowing for the decoding and retirement of up to two times more instructions than its recently launched, 2-way, 223 core. It is also coupled with more functional units, which significantly increases the IPC (instructions-per-cycle).

July 20, 2023
Semidynamics announces, 4-way, Atrevido 423 RISC-V core

Semidynamics has launched the next member of its Atrevido family of 64-bit cores. The Atrevido 423 has a wider, 4-way pipeline, allowing for the decoding and retirement of up to two times more instructions than its recently launched, 2-way, 223 core. It is also said to be coupled with more functional units, which significantly increases the IPC (instructions-per-cycle).

July 20, 2023
[CHI] Semidynamics Releases Fully Customizable Quad Atrevido 423 RISC-V Core for Big Data Applications

Semidynamics, provider of the only fully customizable RISC-V processor IP, launched the next member of the Atrevido family of 64-bit cores. The Atrevido 423 has a wider 4-way pipeline, allowing up to twice as many instructions to be decoded and retired as the recently introduced 2-way 223 core. It is also combined with more functional units, greatly increasing the IPC (instructions per cycle).

June 10, 2023
Highlights From RISC-V Summit Europe Point to More RISC-V Abstraction

New innovations from the RISC-V Summit Europe are poised to streamline the design process for open-source processors.
As we wrap up the week of RISC-V Summit Europe, here we'll review how companies this week used the event as a platform to reveal their latest innovations leveraging the open instruction set architecture (ISA). These developments encompass both hardware and software, making them important to designers in a breadth of fields.

June 09, 2023
RISC-V gathers pace in Europe

The RISC-V Summit Europe brought together developers, architects, technical decision and policy makers from across European RISC-V ecosystem for the first time in the region this week.
Attendees from academia, research, SMEs, industry and open source communities  gathered in Barcelona to discuss the technologies and research shaping the future of RISC-V computing, in applications such as Automotive, High Performance Computing, AI, and Security.

June 08, 2023
Bruselas autoriza 8.100 millones en ayudas para revitalizar la industria europea de microelectrónica

La Comisión Europea ha dado este jueves luz verde al mayor proyecto europeo de interés común (IPCEI) por el que 14 países de la Unión Europea, incluido España, podrán destinar hasta 8.100 millones de euros en ayudas públicas a iniciativas para el desarrollo de microelectrónica y tecnologías de la comunicación.

June 05, 2023
Customisable RISC-V Vector Unit is largest available, says Semidynamics

At up to 2048bits of computation per cycle, Semidynamics says that its customisable Vector Unit is the largest available in the RISC-V market today, offering “unprecedented data handling”.
At the RISC-V Summit Europe 2023 (05 to 09 June) in Barcelona, Semidynamics highlights the customisable vector unit to accompany the company’s customisable 64-bit RISC-V cores. The Vector Unit complies with the RISC-V Vector Specification 1.0 and has additional, customisable features to enhance data handling capabilities. Semidynamics claimed that together they “set a new standard for data handling both in terms of unprecedented speed and volume”.

June 03, 2023
Semidynamics announces largest, fully customisable Vector Unit in the RISC-V market, delivering up to 2048b of computation per cycle

Semidynamics has equipped its Vector Unit with a high-performance, cross-vector-core network that provides all-to-all connectivity between the vector cores at high bandwidth, even for the very large, 32-vector core option. The cross-vector-core unit is used for specific instructions in the RISC-V standard that shuffle data between the different vector cores, such as vrgather, vslide, etc.

June 02, 2023
RISC-V Summit: Customisable vector unit

Vector unit are composed of several vector cores that perform multiple calculations in parallel.
In this case, Semidynamics’ vector core can be tailored to support FP64, FP32, FP16, BF16, INT64, INT32, INT16 or INT8 data types depending on requirements – the longest word-length implemented defines the vector core width (‘ELEN’).