Spanish RISC-V IP developer Semidynamics has benchmarked the performance of its Tensor Unit running a LlaMA-2 7B-parameter Large Language Model (LLM) on an ‘all in one’ RISC-V AI IP core .

Semidynamics, a European RISC-V custom core AI specialist, has introduced an innovative 'All-In-One' AI IP solution that integrates CPU, Tensor Unit, and Vector Unit into a single scalable processing element. 

Aquestes dades s’han donat a conèixer en la presentació de l’Aliança de semiconductors i xips de Catalunya, que ha comptat amb la presència dels consellers d’Empresa i Treball, Economia i Hisenda i Recerca i Universitats, i d’empreses com Semidynamics, Qilimanjaro, Ideaded o Inbrain

Un sector que agrupa 256 empreses i entitats a casa nostra i genera 4.600 llocs de treball però que necessita deixar enrere la fase del "potencial" per començar a complir amb les promeses de ser "líder" i "referent" en les pròximes dècades.

Roger Espasa is the CEO and founder of Semidynamics, an IP supplier of two RISC-V cores, Avispado (in-order) and Atrevido (out-of-order) supporting the RISC-V vector extension and Gazzillion(tm) misses, both targeted at HPC and Artificial Intelligence.

In a RISC-V CPU, a vector unit, a tensor unit, and a cache protocol - those are the puzzle pieces in Spanish Semidynamics' IP offering All-In-One for an AI parallel processor.

Spanish tech company Semidynamics has rolled out an innovative AI chip design that aims to revolutionize the semiconductor industry by providing a comprehensive all-in-one solution. This design includes a suite of essential components, such as a RISC-V CPU, vector unit, tensor unit, and a cache protocol, needed to build a state-of-the-art AI parallel processor.

Semidynamics takes a non-traditional approach to design enablement. Not long ago, the company’s Founder and CEO, Roger Espasa unveiled extreme customization at the RISC-V Summit. That announcement focused on a RISC-V Tensor Unit designed for ultra-fast AI solutions. Recently, at Embedded World 2024 the company took this...

The All-In-One AI IP bundles a CPU, GPU, NPU—and Semidynamics' unique, in-house "Gazzillion Misses" technology—into a single subsystem.

Barcelona-based Semidynamics is aiming at next-generation AI chips and algorithms such as transformer with intellectual property called All-In-One AI.

Semidynamics, the RISC-V custom core AI specialist, has unveiled its All-In-One AI IP that’s been designed for powerful, next generation AI chips and algorithms such as transformers.

Spanish AI IP supplier SemiDynamics has combined its RISC-V core and AI accelerator blocks into a single package to future proof embedded AI chip design.
SemiDynamics has combined its RISC-V core, vector engine and tensor engines with its interconnect into a single ‘all in one’ element with an open source software layer. This will be launched at the Embedded World show next week in Germany.

Semidynamics, the European RISC-V custom core AI specialist, has announced its ‘All-In-One AI’ IP that is designed for super powerful, next generation AI chips and algorithms such as transformers. Currently, AI chip designers use the approach of integrating separate IP blocks next to the system CPU to handle the ever-increasing demands of AI. Semidynamics has taken a revolutionary approach of a unified solution combining RISC-V, vector, tensor and Gazzillion technology so that AI chips are now easy to program and scale to whatever processing power is required.

AI IP combines four IPs together to form one, integrated solution with fully customizable RISC-V 64-bit core, vector units, Tensor Unit and Gazzillion unit to ensure huge amounts of data can be handled from anywhere in the memory.

Semidynamics introduced its groundbreaking ‘All-In-One AI’ IP tailored for highly advanced AI chips and cutting-edge algorithms like transformers.
Traditionally, AI chip developers have relied on integrating distinct IP blocks alongside the system CPU to meet the escalating AI requirements.

European RISC-V specialist Semidynamics is aiming to deliver a smarter approach to on-device artificial intelligence, by ditching the distinction between central, graphics, and neural processing units (CPUs, GPUs, and NPUs) in favor of a unified approach: the All-In-One AI processing element.

»Configurator« verwendet Dutzende von Blöcken, die Semidynamics bereits verifiziert hat, so dass der endgültige Kern ebenfalls verifiziert ist. Dies ermöglicht es, innerhalb weniger Stunden aus Tausenden von möglichen Varianten einen funktionsfähigen Kern zu entwerfen.

Semidynamics, a company specializing in RISC-V solutions, has introduced the Configurator tool, a resource that equips customers to customize their RISC-V processor cores. This tool aims to change the development cycle in embedded systems and processor design, putting the customization capabilities directly with the customers. It represents a shift in how customers can design the processor cores.

Semidynamics a lancé son nouvel outil appelé « Configurator » qui met entre les mains du client la puissance de la personnalisation complète par Semidynamics d’un cœur de processeur RISC-V.

Semidynamics now offers its new tool, ‘Configurator,’ which puts the power of its full customisation of a RISC-V processor core in the hands of the customer. It uses dozens of blocks that have already been verified by the company, so the final core is also verified. This gives customers an incredible fast time to a workable core design in a few hours from the thousands of possible variants.

Semidynamics has released its new tool called 'Configurator' that puts the power of Semidynamics' full customisation of a RISC-V processor core in the hands of the customer.

Semidynamics has released its new tool called ‘Configurator’ that puts the power of Semidynamics’ full customisation of a RISC-V processor core in the hands of the customer.

Semidynamics in Spain has developed a Web tool for designers to fully configure its RISC-V cores.  

Semidynamics become the only company to offer fully customisable RISC-V IP cores helping customers get ample choices when specifying their requirements.

La société espagnole Semidynamics, spécialiste des cœurs de processeurs RISC-V personnalisés, a lancé « Configurator » son nouvel outil qui permet au client de personnaliser intégralement un cœur de processeur RISC-V. Cet outil utilise des dizaines de blocs validés par Semidynamics, de sorte que le cœur final est vérifié.  Ainsi, le client obtient en quelques heures, un noyau utilisable parmi les milliers de variantes possibles.

Semidynamics, the European RISC-V custom core specialist, has released its new tool called ‘Configurator’ that puts the power of Semidynamics’ full customisation of a RISC-V processor core in the hands of the customer. It uses dozens of blocks that have already been verified by Semidynamics so that the final core is therefore also verified. This gives customers an incredible fast time to a workable core design in a matter of a few hours from the thousands of possible variants.

In an innovative leap forward, Semidynamics in Spain has launched a groundbreaking Configurator tool that revolutionizes the way developers design RISC-V cores. This web-based tool, a first in offering full customization of RISC-V IP cores, allows for intricate core design configuration via a user-friendly interface, promising a new era of microprocessor development.

Semidynamics, the European RISC-V custom core specialist, has released its new tool called ‘Configurator’ that puts the power of Semidynamics’ full customisation of a RISC-V processor core in the hands of the customer. It uses dozens of blocks that have already been verified by Semidynamics so that the final core is therefore also verified. This gives customers an incredible fast time to a workable core design in a matter of a few hours from the thousands of possible variants.

Collaborative activity in Europe last year underscored this trend. For example, Semidynamics partnered with Signature IP to produce a fully tested RISC-V, multicore environment and coherent hub interface (CHI) interconnect for the development of state-of-the-art chip designs. Semidynamics’ new RISC-V Tensor Unit combines the company’s core vector unit and an array unit, eliminating the need to purchase separate NPUs, GPUs or additional components.

YorChip unveils first Chiplet for Edge AI applications

YorChip has unveiled its first Chiplet for Edge AI applications with IP licensed from Semidynamics, the RISC-V IP specialists.

Edge AI chiplet uses SemiDynamics RISC-V cores

YorChip is developing a chiplet for edge AI applications using RISC-V cores from Semidynamics in Barcelona

YorChip, Inc. announces its first Chiplet for Edge AI applications with IP licensed from Semidynamics, the leader in RISC-V IP based in Barcelona

YorChip, Inc. announces its first Chiplet for Edge AI applications with IP licensed from Semidynamics, the leader in RISC-V IP based in Barcelona

YorChip Edge AI Compute Chiplet with support for UCIe and 10-100+ Int8-TOPS

Founded in 2016 and based in Barcelona, Spain, Semidynamics™ is the only provider of fully customizable RISC-V processor IP.  The company delivers high bandwidth, high performance cores with vector units and tensor units targeted at machine learning and AI applications. There were some recent announcements from Semidynamics leading up to the RISC-V Summit that extend the company’s focus on customization. I had a chance to meet with the company’s CEO at the Summit to get the back-story on what the announcement really means. Read on to get the whole story about how Semidynamics founder and CEO, Roger Espasa, introduces extreme customization.

Arteris, Inc. and Semidynamics are collaborating to enhance the next generation of electronic components for artificial intelligence (AI), machine learning (ML) and high-performance computing (HPC) applications. The agreement sees the interoperability between Semidynamics' Atrevido and Avispado 64-bit RISC-V processor IP cores and Arteris’ Ncore cache coherent network-on-chip (NoC) system IP.

The European Processor Initiative (EPI), a project with 30 partners from 10 European countries, with the goal of achieving Europe’s independence in HPC chip technologies and infrastructure, has announced the successful Manufacturing and Silicon Demonstration of its EPAC Accelerator chip version 1.5.

Also today, Semidynamics announced the launch of its first fully-coherent RISC-V Tensor unit that the company says will not only reduce latency, processor cycles and energy use, it will also, when married to the Vector regulators, solve the memory wall problem. Roger Espasa, CEO & Founder at Semidynamics Technology Services, said the full system is designed to be ideal for AI and machine learning embedded systems, thanks to the new Tensor unit, and the company’s customizable 64-bit cores, married to the vector regulators, Gazzillion data management software, and the unique architecture that brings all these units together in one piece.

Collaboration with Signature IP yields multicore environment and CHI interconnect customizable for performance and optimizable for efficiency.
Customizability and scalability are among the most common requirements of artificial intelligence and machine learning applications. AI and ML regularly involve complex algorithms and require specialized hardware and software optimizations that promote high performance and efficiency.

California, Campbell - November 2, 2023 - Arteris, Inc. (NASDAQ: AIP) is a leading system IP provider dedicated to accelerating the creation of System-on-Chips (SoCs). Semidynamics is a fully customizable high-bandwidth and high-performance RISC-V processor IP provider. Arteris and Semidynamics announced today the establishment of a partnership to accelerate electronic product innovation for Artificial Intelligence (AI), Machine Learning (ML), and High-Performance Computing (HPC) applications.
This partnership supports the interoperability between Semidynamics' Atrevido™ and Avispado™ 64-bit RISC-V processor IP cores and Arteris' Ncore high-speed Cache Coherent Network-on-Chip (NoC) system IP. This combined solution offers interoperability to expedite the development of AI/ML and HPC designs.

Arteris, Inc. (NASDAQ: AIP) is a leading system IP provider dedicated to accelerating the creation of System-on-Chips (SoCs). Semidynamics is a fully customizable high-bandwidth and high-performance RISC-V processor IP provider. Arteris and Semidynamics announced today the establishment of a partnership to accelerate electronic product innovation for Artificial Intelligence (AI), Machine Learning (ML), and High-Performance Computing (HPC) applications.

Arteris, a provider of system IP which accelerates SoC design, and Semidynamics, a provider of fully customisable high bandwidth and high-performance RISC-V processor IP, have partnered to accelerate electronic product innovation for AI, ML and HPC applications.
The partnership supports the interoperability between Semidynamics’ Atrevido and Avispado 64-bit RISC-V processor IP cores and Arteris’ Ncore cache coherent network-on-chip (NoC) system IP.

Intended for use in ultra-fast artificial intelligence (AI) implementations, a RISC-V Tensor Unit has just been introduced by Semidynamics.
Relying on the company’s configurable 64-bit cores, this presents customers with hardware that is highly optimised to meet the requirements of matrix multiplication workloads. The result is a solution that can handle intense computation demands while still keeping the power budget involved to a minimum. 

LLM- eli suurten kielimallien merkitys näkyy nyt kaikkialla. Nämä mallit kuten LLaMa-2 tai ChatGPT koostuvat miljardeista parametreista ja vaativat suuren laskentatehon. Tähän useiden biljoonien toimintojen laskentakykyyn pitää pystyä alhaisella energiankulutuksella. Enpanjalaisen Semidynamicsin mukaan RISC-V on laskentaan sopiva alusta.

Optimised for its 64-bit fully customisable RISC-V cores
Semidynamics has just announced a RISC-V Tensor Unit that is designed for ultra-fast AI solutions and is based on its fully customisable 64-bit cores.

Based on Semidynamics’ 64bit customisable RISC-V cores, the RISC-V Tensor Unit is designed for fast AI solutions, said the company.
It can address the need for computation power in applications such as the LLaMa-2 or ChatGPT machine learning models. These consist of billions of parameters and require a large degree of computation power – in the order of several trillions of operations per second. There is also the requirement to keep energy consumption low which poses a significant challenge for hardware design, said Semidynamics. 

Semidynamics has launched the RISC-V Tensor Unit designed for high-speed AI applications, leveraging its adaptable 64-bit cores. Modern machine learning models, like LLaMa-2 or ChatGPT, boast billions of parameters and necessitate computational capabilities to tune several trillion operations every second. Balancing this immense processing demand with energy efficiency is a formidable task in hardware engineering. 

Il existe aujourd’hui une demande croissante pour des puces toujours plus puissantes pour des applications avancées telles que l'intelligence artificielle (IA) et l’apprentissage automatique (ML), technologies qui nécessitent souvent plusieurs cœurs sur une seule puce. Pour faciliter cette évolution en particulier pour des puces RISC-V multicœurs, les sociétés Semidynamics et SignatureIP se sont associées pour intégrer leurs IP respectives afin de fournir un environnement multicœur RISC-V entièrement testé, ainsi qu’une interconnexion CHI (Coherent Hub Interface) pour la conceptions de puces complexes.

Optimised for its 64-bit fully customisable RISC-V cores.
Semidynamics has just announced a RISC-V Tensor Unit that is designed for ultra-fast AI solutions and is based on its fully customisable 64-bit cores.

Semidynamics has announced a RISC-V Tensor Unit that is designed for ultra-fast AI solutions and is based on its fully customisable 64-bit cores.
State-of-the-art Machine Learning models, such as LLaMa-2 or ChatGPT, consist of billions of parameters and require a large computation power in the order of several trillions of operations per second. Consequently, delivering such massive performance while keeping energy consumption low is a significant challenge for hardware design.

SemiDynamics in Spain has developed a RISC-V Tensor Unit for AI chip design based on its fully customisable 64bit cores.
The RISC-V Tensor unit is integrated into the cache sub-system, which SemiDynamics makes it the first fully coherent such unit for high performance AI chip design in the data centre.

Semidynamics has just announced a RISC-V Tensor Unit that is designed for ultra-fast AI and is based on its fully customisable 64-bit cores.

A new RISC-V Tensor Unit, based on fully customizable 64-bit cores, claims to provide a huge performance boost for artificial intelligence (AI) applications compared to just running software on scalar processors. The Tensor Unit provides matrix multiplications required by AI applications via a hardware design that delivers massive compute performance while keeping energy consumption low.

Semidynamics i Barcelona lanserar en neuronkärna baserad på den fria arkitekturen Risc V. Samtidigt presenterar företaget en processorarkitektur för artificiella neuronnät.
Neuronkärnan (omväxlande kallad NPU och TPU, tensorenhet) är inte Semidynamics första Risc V-baserade kärna. Företaget har sedan tidigare en VPU (Vector Processing Unit) och två 64-bitars CPU:er – allt baserat på Risc V.

Two relatively new players in the CPU world, Semidynamics and Signature IP, have announced multi-core RISC-V and CHI interconnect IP for compute-intensive applications like AI/ML.
As some experts predict the end of Moore’s law, the artificial intelligence and machine learning (AL/ML) industry needs to find ways to greatly increase computing power density and efficiency. Such gains call for monolithic multi-core and chiplet architectures and improved interconnects.

Semidynamics has collaborated with Californian start-up SignatureIP on the creation of a fully-tested interoperable RISC-V, multi-core environment plus CHI interconnect.
It draws on the companies’ respective customisable 64-bit RISC-V processing IP and Coherent NoC IP elements. Consequently, this will be able to help speed-up and de-risk next generation chip design projects - so that demanding artificial intelligence (AI) workloads can be dealt with. SignatureIP’s Coherent NoC IP delivers strong performance alongside inherent scalability. It supports a transport layer for chiplet communication. Semidynamics’ multi-core architecture provides an easily configurable platform for designers to work with.  

Semidynamics and SignatureIP are collaborating to incorporate respected technologies for a completely assessed multi-core RISC-V environment and CHI interconnect for innovations in chip development for AI and ML applications. The solution utilizes SignatureIP’s Coherent NoC, designed to be scalable with the inclusion of a transport layer for chiplet communication and acts as an ordered file system with support for home-node resource group.

There is an ever-increasing demand for more powerful chip designs for advanced applications, such as AI and ML, that require many cores on one chip and RISC-V technology is particularly suitable for such requirements.
To facilitate this, Semidynamics and SignatureIP have partnered to integrate their respective IPs to provide a fully-tested RISC-V, multi-core environment and CHI interconnect for the development of state-of-the-art chip designs.

Semidynamics in Spain has teamed up with SignatureIP in the US to combine multi-core RISC-V IP with CHI interconnect for the development of the latest chiplet AI chips.
SignatureIP’s Coherent network on chip (NoC) IP is designed for chiplet designs and supports a transport layer for chiplet communication using ARM’s Coherent Hub Interface (CHI) interconnect standard.

There is an ever-increasing demand for more powerful chip designs for advanced applications, such as AI and ML, that require many cores on one chip. To facilitate this, Semidynamics and SignatureIP have partnered to integrate their respective IPs to provide a fully-tested RISC-V, multi-core environment and CHI interconnect for the development of state-of-the-art chip designs.

There is an ever-increasing demand for more powerful chip designs for advanced applications, such as AI and ML, that require many cores on one chip. To facilitate this, Semidynamics and SignatureIP have partnered to integrate their respective IPs to provide a fully-tested RISC-V,  and CHI interconnect for the development of state-of-the-art chip designs.

There is an ever-increasing demand for more powerful chip designs for advanced applications, such as AI and ML, that require many cores on one chip. To facilitate this, Semidynamics and SignatureIP have partnered to integrate their respective IPs to provide a fully-tested RISC-V, multi-core environment and CHI interconnect for the development of state-of-the-art chip designs.

There is an ever-increasing demand for more powerful chip designs for advanced applications, such as AI and ML, that require many cores on one chip. To facilitate this, Semidynamics and SignatureIP have partnered to integrate their respective IPs to provide a fully-tested RISC-V, multi-core environment and CHI interconnect for the development of state-of-the-art chip designs.

Semidynamics launched a fully customisable 64-bit RISC-V core, Atrevido 423,  for big data applications. The core can be opened up to insert a customer’s specific instructions which the company calls Open Core Surgery.

RISC-V as an Instruction Set Architecture (ISA) has grown quickly in commercial importance and relevance since its release to the open community in 2015, attracting many IP vendors that now provide a variety of RTL cores. Roger Espasa, CEO and Founder of Semidynamics, has presented at RISC-V events on how their IP is customized for compute challenges that require high bandwidth and high performance cores with vector units. 

Neil Tyler talks to the CEO and founder of Semidynamics and looks at the core architecture they have developed for the RISC-V community.

Semidynamics, provider of the only fully customizable RISC-V processor IP, unveils the next member of the Atrevido family of 64-bit cores. The Atrevido 423 has a wider 4-way pipeline, allowing up to twice as many instructions to be decoded and retired as the recently introduced 2-way 223 core. It is also combined with more functional units, which greatly increases the IPC (instructions per cycle).

Semidynamics, the only provider of fully customisable RISC-V processor IP, has launched the next member of its Atrevido family of 64-bit cores. The Atrevido 423 has a wider, 4-way pipeline, allowing for the decoding and retirement of up to two times more instructions than its recently launched, 2-way, 223 core. It is also coupled with more functional units, which significantly increases the IPC (instructions-per-cycle).

Semidynamics, currently the only provider of fully customisable RISC-V processor IP, has launched the next member of its Atrevido family of 64-bit cores.

Soooo… you’ve decided you’re going to create a system-on-chip (SoC) device of such awesomeness that it will leave your competitors gnashing their teeth and rending their garb. You’ve also decided to base this on a RISC-V processor. What you want is the biggest, baddest RISC-V processor going. Furthermore, you want this processor to be customized to allow you to take full advantage of your own “secret sauce” IP. Who ya gonna call?

The Atrevido 423 RISC-V core has a wide 4-way pipeline for decoding and retiring twice as many instructions as the previous 2-way 223 core. It is also coupled with more functional units, which significantly increases the instructions-per-cycle (IPC) throughput.

Semidynamics, the only provider of fully customisable RISC-V processor IP, has launched the next member of its Atrevido family of 64-bit cores. The Atrevido 423 has a wider, 4-way pipeline, allowing for the decoding and retirement of up to two times more instructions than its recently launched, 2-way, 223 core. It is also coupled with more functional units, which significantly increases the IPC (instructions-per-cycle).

Semidynamics has launched the next member of its Atrevido family of 64-bit cores. The Atrevido 423 has a wider, 4-way pipeline, allowing for the decoding and retirement of up to two times more instructions than its recently launched, 2-way, 223 core. It is also said to be coupled with more functional units, which significantly increases the IPC (instructions-per-cycle).

Semidynamics, provider of the only fully customizable RISC-V processor IP, launched the next member of the Atrevido family of 64-bit cores. The Atrevido 423 has a wider 4-way pipeline, allowing up to twice as many instructions to be decoded and retired as the recently introduced 2-way 223 core. It is also combined with more functional units, greatly increasing the IPC (instructions per cycle).

The exclusive provider of fully customizable RISC-V processor IP, Semidynamics, has launched the next member of the Atrevido series 64-bit cores. Atrevido 423 features a wider 4-stage pipeline, allowing decoding and retiring of instructions twice as high as the recently launched 2-stage 223 core. It also integrates more functional units, significantly increasing the IPC (Instructions Per Cycle).

完全可定制的RISC-V处理器IP的提供商Semidynamics推出了Atrevido系列64位内核的下一个成员。Atrevido 423具有更宽的4路管道，允许解码和退役的指令最高是最近推出的2路223内核的两倍。它还与更多功能单元结合，大幅增加了IPC（每周期指令数）。

Calista Redmond, CEO of RISC-V International, joins Roger Espasa, Founder and CEO of Semidynamics, to discuss their new vector unit, making processors go fast in HPC and AI applications, and plans for the future.

The RISC-V Instruction Set Architecture is perfectly suitable for fine tuning the performance depending on the application. In this interview Roger Espasa, CEO and Founder at Semidynamics Technology Services explains how cores and vectorizing can be used to build ‘Tailor Made’ client specific silicon.

Spanish start-up Semidynamics announced the launch of the RISC-V Vector Unit (Vector Unit) that can be used for highly parallel processors such as artificial intelligence (AI), high-performance computing (HPC) and even graphics. This is the development of the RISC-V ecosystem

Capable of delivering up to 2048b of computation per cycle, the new Vector Unit from Semidynamics is a completely customisable platform that accompanies the company’s 64-bit RISC-V core offering.

New innovations from the RISC-V Summit Europe are poised to streamline the design process for open-source processors.
As we wrap up the week of RISC-V Summit Europe, here we'll review how companies this week used the event as a platform to reveal their latest innovations leveraging the open instruction set architecture (ISA). These developments encompass both hardware and software, making them important to designers in a breadth of fields.

The RISC-V Summit Europe brought together developers, architects, technical decision and policy makers from across European RISC-V ecosystem for the first time in the region this week.
Attendees from academia, research, SMEs, industry and open source communities  gathered in Barcelona to discuss the technologies and research shaping the future of RISC-V computing, in applications such as Automotive, High Performance Computing, AI, and Security.

La Comisión Europea ha dado este jueves luz verde al mayor proyecto europeo de interés común (IPCEI) por el que 14 países de la Unión Europea, incluido España, podrán destinar hasta 8.100 millones de euros en ayudas públicas a iniciativas para el desarrollo de microelectrónica y tecnologías de la comunicación.

Semidynamics is a European provider of RISC-V based solutions, specializing in the development of high performance cores and high bandwidth with vector drives targeting applications of machine learning and artificial intelligence. The company has just announced one of the first RISC-V vector drives of the sector. A unit of vector processing is designed to perform parallel operations on data vectors, allowing high performance for a wide range of computationally intensive applications. Think of real-time image processing, the machine learningscientific simulation and much more.

Configurable high-bandwidth RISC-V cores with vector units can be made to directly address challenging applications like machine learning, AI, and other cutting-edge spaces.

Semidynamics delivers a fully customizable Vector Unit integrated into 64-bit RISC-V cores able to run up to 2048b of computation per cycle for large data transmissions. The unit follows the RISC-V Vector Specification 1.0 and adds many features to fit user requirements.

RISC-V vector unit: what it is and why the one from Semidynamics can revolutionize the market
After having accumulated an abysmal gap against the tech giants with headquarters in other continents, the European Union wishes to return to the leading role in the development and production of microprocessors.

Semidynamics has introduced one of the industry's first RISC-V vector units available for use in highly parallel processors such as those used in artificial intelligence (AI), high performance computing (HPC) and even graphics (if equipped with the appropriate dedicated processor ) destination IP. This announcement marks an important milestone in the development of the RISC-V ecosystem.

Semidynamics has introduced one of the industry's first RISC-V vector units that could be used for highly parallel processors, such as those used for artificial intelligence (AI), high-performance computing (HPC), and even graphics processing if equipped with appropriate special-purpose IP. The announcement marks an important milestone in the development of the RISC-V ecosystem. 

La ISA RISC-V está de moda. Este fin de semana hemos visto cómo grandes compañías se suman a crear chips con ella, y no debería ser algo novedoso como tal, pero como se suele decir, la moda es la moda. Otras compañías con no tanto bombo y platillo llevan tiempo trabajando con esta ISA, como Semidynamics, que ha presentado su nueva Unidad Vectorial, la más grande y completa del mercado con la friolera de 2.048 bits.

The Spanish company Semidynamics shows that the open RISC-V architecture is rapidly catching up with other processor architectures that have been on the market longer. The company's latest vector unit brings a computing capacity of up to 2048 bits per clock cycle.

A semi-dynamic tem introduzido uma das primarsa unidades vetoriais RISC-V do Setor que pode ser usada para procesadores highly paralelos, Como os usados para intelligencia artificial (IA), computação de alto perfomance (HPC) e even mesmo processing graphic, se equipado com IP appropriate para fins especiales . O announcement marca um marco importante no desenvolvimento do ecossistema RISC-V.

At up to 2048bits of computation per cycle, Semidynamics says that its customisable Vector Unit is the largest available in the RISC-V market today, offering “unprecedented data handling”.
At the RISC-V Summit Europe 2023 (05 to 09 June) in Barcelona, Semidynamics highlights the customisable vector unit to accompany the company’s customisable 64-bit RISC-V cores. The Vector Unit complies with the RISC-V Vector Specification 1.0 and has additional, customisable features to enhance data handling capabilities. Semidynamics claimed that together they “set a new standard for data handling both in terms of unprecedented speed and volume”.

Semidynamics has equipped its Vector Unit with a high-performance, cross-vector-core network that provides all-to-all connectivity between the vector cores at high bandwidth, even for the very large, 32-vector core option. The cross-vector-core unit is used for specific instructions in the RISC-V standard that shuffle data between the different vector cores, such as vrgather, vslide, etc.

Vector unit are composed of several vector cores that perform multiple calculations in parallel.
In this case, Semidynamics’ vector core can be tailored to support FP64, FP32, FP16, BF16, INT64, INT32, INT16 or INT8 data types depending on requirements – the longest word-length implemented defines the vector core width (‘ELEN’).

Arm mobile platform; making software for RISC-V; GPU AI supercomputer; scaling up batteries.

Semidynamics has announced its new, entirely customisable Vector Unit to go with its innovative range of fully customisable 64-bit RISC-V cores. The Vector Unit is totally compliant with the RISC-V Vector Specification 1.0 with many, additional, customisable features to provide enhanced data handling capabilities. Together they set a new standard for data handling both in terms of unprecedented speed and volume.

Vector unit are composed of several vector cores that perform multiple calculations in parallel.
In this case, Semidynamics’ vector core can be tailored to support FP64, FP32, FP16, BF16, INT64, INT32, INT16 or INT8 data types depending on requirements – the longest word-length implemented defines the vector core width (‘ELEN’).

Semidynamics in Spain has developed a highly configurable out of order vector unit with a new architecture to boost performance of RISC-V processor designs, and is running a demonstration of Doom.
The Vector Unit pairs with Semidynamics’ 64bit Out-Of-Order RISC-V Atrevido core and upcoming In-Order cores. “We are launching the configurable core with the vector unit support,” Roger Esposa, CEO of SemiDynamics tells eeNews Europe.

Semidynamics has announced its new, entirely customisable Vector Unit to go with its innovative range of fully customisable 64-bit RISC-V cores. The Vector Unit is totally compliant with the RISC-V Vector Specification 1.0 with many, additional, customisable features to provide enhanced data handling capabilities. Together they set a new standard for data handling both in terms of unprecedented speed and volume.

Semidynamics has announced a customisable vector unit for RISC-V processor cores, compliant with RISC-V vector specification 1.0.

Vector unit are composed of several vector cores that perform multiple calculations in parallel.

Semidynamics has announced its new, fully customizable vector unit to accompany its innovative family of fully customizable 64-bit RISC-V cores. The vector unit is fully compliant with the RISC-V vector specification 1.0, with many additional, customizable features to provide enhanced data processing capabilities. Together, they set new standards for data processing at unprecedented speed and volume.

Semidynamics has announced its new, entirely customisable Vector Unit to go with its innovative range of fully customisable 64-bit RISC-V cores. The Vector Unit is totally compliant with the RISC-V Vector Specification 1.0 with many, additional, customisable features to provide enhanced data handling capabilities. Together they set a new standard for data handling both in terms of unprecedented speed and volume.

Semidynamics has released a customizable vector unit to accompany the 64bit RISC-V processor cores the company has designed for high-performance computing systems.

Semidynamics has announced its new, fully customizable vector unit to accompany its innovative family of fully customizable 64-bit RISC-V cores. The vector unit is fully compliant with the RISC-V vector specification 1.0, with many additional, customizable features to provide enhanced data processing capabilities. Together, they set new standards for data processing at unprecedented speed and volume.

After having accumulated an abysmal gap against the tech giants with headquarters in other continents, the European Union wishes to return to the leading role in the development and production of microprocessors. On the one hand, the Chips Act aims to bring at least 20% of global semiconductor production to Europe: from this point of view, Intel itself has decided to strengthen its presence in the Old Conti....

Semidynamics offers fully customized RISC–V CPUs for clients requiring capabilities beyond what’s readily available. The ability to maintain many outstanding memory requests boosts performance for applications with poor data locality.

Roger Espasa, CEO of SemiDynamics, discusses the technology behind the company’s fully configurable 64-bit, RISC-V processor IP, the recent launch of the Atrevido core – the first in a fully customisable 64-bit RISC-V family of cores, focusing on demanding machine learning and AI applications.

Semidynamics announced a family of customizable 64-bit RISC-V IP cores optimized for handling large amounts of data in applications such as AI/ML and HPC.

Semidynamics has released the world’s first, fully customisable, 64-bit RISC-V family of cores that are excellent for handling large amounts of data for applications, including AI, ML and HPC. The cores are process agnostic, with versions currently supplied down to 5nm.

The Spanish startup Semidynamics has developed commercial 64-bit RISC-V IP cores that can be adapted to a target application in all parameters. The cores are not tied to specific manufacturing processes and target compute-intensive applications such as artificial intelligence and machine learning with high bandwidth and vector units.

Startup SemiDynamics has come out of stealth mode to introduce what it said is the first fully customizable, 64-bit RISC-V core family for handling large amounts of data for ML, AI, and HPC.

Semidynamics, the only provider of fully configurable RISC-V processor IP, has announced the world’s first, fully customisable, 64-bit RISC-V family of cores that are ideal for handling large amounts of data for applications such as AI, Machine Learning (ML) and High-Performance Computing (HPC). The cores are process agnostic with versions already being supplied down to 5nm.

At its heart, the RISC-V movement centers around the idea of democratizing processor design. With an open-source instruction set architecture (ISA) and a plethora of resources available to anyone free of cost, RISC-V is meant to enable any company, regardless of resources, to design custom hardware.

Crée en 2016 à Barcelone, le concepteur espagnol de semiconducteurs sans fabrication  Semidynamics a annoncé la première famille de cœurs RISC-V 64 bits entièrement personnalisable, idéale pour traiter les  traiter les grandes quantités de donnés des applications ce l’IA, de l’apprentissage automatique (ML) et du calcul à haute performance (HPC). Ces cœurs ne dépendent d’aucun processus et des versions jusqu’à 5 nm sont déjà disponibles.

Semidynamics, the only provider of fully configurable RISC-V processor IP, announced the world's first fully customizable 64-bit RISC-V family of cores for artificial intelligence, machine learning (ML) and high-performance Ideal for processing large amounts of data in applications such as computing (HPC). These cores are process agnostic and are already available down to 5nm.

Semidynamics, the only provider of fully configurable RISC-V processor IP, has announced the world’s first, fully customisable, 64-bit RISC-V family of cores that are ideal for handling large amounts of data for applications such as AI, Machine Learning (ML) and High-Performance Computing (HPC). The cores are process agnostic with versions already being supplied down to 5nm.

Spanish startup SemiDynamics has developed fully configurable 64bit RISC-V processor IP for high performance chip designs in AI, Machine Learning (ML) and High-Performance Computing (HPC).

Semidynamics, fabricante de procesadores RISC-V completamente configurables con propiedad intelectual, anuncia el lanzamiento de la primera familia de núcleos RISC-V de 64 bits completamente personalizables.

Semidynamics, a Barcelona-based provider of fully configurable RISC-V processor IP, has announced the world’s first, fully customisable, 64-bit RISC-V family of cores.

Semidynamics has announced the first, fully customisable, 64-bit RISC-V family of cores that are ideal for handling large amounts of data for applications such as AI, Machine Learning (ML) and High-Performance Computing (HPC). The cores are process agnostic with versions already being supplied down to 5nm.

Semidynamics released a one of a kind 64-bit RISC-V family of cores boosting the ability to transmit copious amounts of information for high-performance computing (HPC) and AI/ML. The cores are process agnostic and utilize Gazzillion technology that was developed for recommendation systems, a must for data center ML.

Semidynamics, the only provider of fully configurable RISC-V processor IP, has announced the world’s first, fully customisable, 64-bit RISC-V family of cores that are ideal for handling large amounts of data for applications such as AI, Machine Learning (ML) and High-Performance Computing (HPC). The cores are process agnostic with versions already being supplied down to 5nm.

Semidynamics, a well-known European RISC-V IP core supplier, announced the world's first fully customizable 64-bit RISC-V core series for artificial intelligence, machine learning (ML) and high-performance computing (HPC) ) provide an ideal choice for processing large amounts of data.

Semidynamics released a one of a kind 64-bit RISC-V family of cores boosting the ability to transmit copious amounts of information for high-performance computing (HPC) and AI/ML. The cores are process agnostic and utilize Gazzillion technology that was developed for recommendation systems, a must for data center ML.

Barcelona-based Semidynamics has launched RISC-V processor IP that the company claims provides a great deal more customisability than other off-the-shelf cores on the market and which incorporates a novel memory unit that improves performance on the kinds of sparse data structures used in some machine-learning applications.

Thirty semiconductor and electronics companies in Europe that felt they were in crisis formed an alliance called EPI (European Processor Initiative) to develop their own CPUs and GPUs.

The Catalan semiconductor industry is also under intense development. Europe is doing more to promote the semiconductor field due to the perception that the United States, Korea and Taiwan are leaving it behind in terms of semiconductor factories and design. To overcome this situation, European countries, including Spain, are receiving EU aid under the "EPI Project," which supports semiconductor design companies.

Move comes ahead of draft law to turn continent into a center of semiconductor expertise

Additional €43bn in the pipeline, but it's still chickenfeed, say critics

L'European Processor Initiative, qui réunit 28 acteurs technologiques de l'UE pour concevoir un processeur HPC européen, a présenté ses 1ers résultats. Outre les spécifications architecturales du Rhea, 1ère génération du processeur universel de l'EPI, le projet a réalisé une preuve de concept d'un accélérateur et un microcontrôleur haute performance embarqué pour les applications de la filière automobile.

Three years of R&D and design work to be tested with plans to build native ‘super in 2023

sureCore, the Sheffield low-power memory IP house, has designed a power and area efficient, high performance, multi-port, embedded memory solution for Semidynamics’ new RISC-V-based, tensor processing chip.

Semidynamics is developing a high bandwidth, vector processing unit optimised for tensor processing aimed at AI applications.

Embedded memory IP specialist sureCore has developed a high performance, multi-port, embedded memory for a RISC-V-based, tensor processing chip.

sureCore, the embedded memory specialist, has designed a power and area efficient, high performance, multi-port, embedded memory solution for Semidynamics’ new RISC-V-based, tensor processing chip.

The EPI was founded by the European Union with the aim of giving the different countries of the old continent total independence of high-performance computing technology from the United States and the great Asian powers. The geopolitical objective is nothing more than to have technological neutrality in a market that is moving to form two large blocks that in the end will end up giving companies to choose between one block or another.

Ya tenemos un chip europeo que ha mostrado en pantalla el célebre "Hello World". Se trata de EPAC (European Processor ACcelerator), un chip con arquitectura RISC-V que ha pasado las primeras pruebas de validación y que está orientado a ser usado en el ámbito de la supercomputación.

In 2018, Europe launched the European Processor Initiative (EPI), which aims to increase the independence of the European supercomputing industry from foreign technology companies. Its core is the use of free and open source RISC-V instruction set architecture for the development and production of high-performance chips in Europe, providing the European Union with independence in the field of high-performance computing (HPC).

The European Processor Initiative (EPI) has run the successful first test of its RISC-V-based European Processor Accelerator (EPAC), touting it as the initial step towards homegrown supercomputing hardware.

The European Processor Initiative (EPI) a project with 28 partners from 10 European countries, with the goal of making EU achieve independence in HPC chip technologies and HPC infrastructure, is proud to announce that EPAC1.0 RISC-V Test Chip samples were delivered to EPI and initial tests of their operation were successful.

European Processor Initiative (EPI) has been working on providing independence for the European Union in the high-performance computing (HPC) field, by developing custom RISC-V-based accelerators. Called the European Processor Accelerator (EPAC) chip, designed for high efficiency and high throughput computation, it has been successfully taped out and is being tested at EPI's labs.