Events
Upcoming Events
CHIPNATION
Dec 02, 2024 | Caixa Forum - Valencia - Spain
The Spanish Association of the Semiconductor Industry (AESEMI) and VASIC (Valencia Silicon Cluster) are organizing the second edition of CHIPNATION, the leading congress for the semiconductor industry in Spain. It will take place in Valencia on December 2nd and 3rd, 2024, at Caixaforum Valencia.
This event will be a unique opportunity to connect with experts, companies, and professionals in the sector, and explore the latest trends and advances in the semiconductor industry.
This event will be a unique opportunity to connect with experts, companies, and professionals in the sector, and explore the latest trends and advances in the semiconductor industry.
ICCAD-Expo China 2024
Dec 11, 2024 | Shanghai World Expo Exhibition & Convention Center - Shanghai
The China Integrated Circuit Design Industry Exhibition (ICCAD-Expo) has always played an important role in promoting industrial agglomeration, connecting industrial resources, and grasping industry trends. It has been held for 29 times and has become one of the most influential industry events in China’s semiconductor industry.
HiPEAC 2025
Jan 20, 2025 | Barcelona - Palau de Congressos, Spain
The HiPEAC conference is the premier European forum for experts in computer architecture, programming models, compilers and operating systems for general-purpose, embedded and cyber-physical systems. Areas of focus and integration include safety-critical dependencies, cybersecurity, energy efficiency and machine learning.
Previous Events
RISC-V Summit North America 2024
Oct 22, 2024 | Santa Clara, California
This October, the global RISC-V community – including technical, industry, domain, ecosystem and special interest groups who define the architecture’s specifications – will meet in Santa Clara, California to share technology breakthroughs, industry milestones, and case studies, as well as to network and build relationships. Come be part of the RISC-V movement.
EPI Forum
Oct 09, 2024 | Barcelona - Spain
The European Processor Initiative is announcing its annual EPI Forum. It is to be held on 9 and 10 October, 2024, in Barcelona, Spain.
EPI Forum will gather experts from the HPC ecosystem, stakeholders in the field and EPI researchers and engineers to discuss and present EPI’s achievement so far and future developments in the Initiative.
EPI Forum will gather experts from the HPC ecosystem, stakeholders in the field and EPI researchers and engineers to discuss and present EPI’s achievement so far and future developments in the Initiative.
RISC-V Summit China 2024
Aug 21, 2024 | The Dragon Hotel Hangzhou - China
RISC-V Summit China has become one of the world’s three major RISC-V professional exhibitions and the largest RISC-V annual event in China. This year, it is expected to attract more than 3,000 domestic and foreign attendees to participate in-person and more than 500k viewers to watch online. At the same time, it is expected that more than 100 companies, research institutions, and open source technology communities will participate. The summit is being held in Hangzhou, Zhejiang for the first time since its establishment in 2021.
RISC-V Day Tokyo Summer 2024
Aug 01, 2024 | Ito International Research Center, The University of Tokyo
The RISC-V Day Tokyo conference is the largest RISC-V event in Japan. The RISC-V Day Tokyo 2024 Winter conference will be held on Tuesday, August 1, 2024 from 9:00-18:00 JST (UTC+9) at the Ito International Research Center, The University of Tokyo. We will bring together excellent RISC-V-related technologies and products, as well as key people and engineers, and provide business opportunities such as increasing product awareness, realizing collaboration between companies, technology exchange, and information gathering.
RISC-V Summit Europe 2024
Jun 24, 2024 | Munich
The RISC-V Summit Europe is the premier event that connects the European movers and shakers - from industry, government, research, academia and ecosystem support - that are building the future of innovation on RISC-V.
IOT World Congress, Aliança Catalana Semiconductors
May 21, 2024 | BARCELONA - GRAN VIA VENUE
Discover the ultimate tech-powered revolution at the IOT Solutions World Congress, the unrivaled event for transformative solutions.
Embedded World 2024
Apr 09, 2024 | Nüremberg
The embedded world Exhibition&Conference provides a global platform and a place to meet for the entire embedded community, including leading experts, key players and industry associations.
SEMICON Japan 2023
Dec 13, 2023 | Tokyo Big Sight, Japan
SEMICON Japan is a premier international exhibition offering the latest insights into the electronics manufacturing and design supply chain. The SEMICON Japan 2022 Opening Ceremony was held on Wednesday, December 14, 2022, from 10:15 a.m. at SuperTHEATER, East Hall 2, Tokyo Big Sight.
RISC-V Summit North America 2023
Nov 06, 2023 | Santa Clara, California
This November, the global RISC-V community – including technical, industry, domain, ecosystem and special interest groups who define the architecture’s specifications – will meet in Santa Clara, California to share technology breakthroughs, industry milestones, and case studies to network and build relationships and to experience much more.
The 25th Semiconductor Exhibition (SEDEX 2023)
Oct 25, 2023 | Coex Seoul, Korea
The Semiconductor Exhibition will be held at COEX from October 25 to 27, 2023. It is among one of the most outstanding exhibitions that covers the full spectrum of the semiconductor industry supply chain. No other event in the world showcases a full range of semiconductor products including SoC, IP, Memory, sensor, equipment/components and materials, and semiconductor technologies for Digital TV, mobile and IoT.
RISC-V Summit China 2023
Aug 23, 2023 | Beijing, China
Under the global leadership of the RISC-V International (RVI), Beijing Institute of Open Source Chip (BOSC) will hold the third annual RISC-V Summit China from Aug 23 to 25, 2023. Save the dates! RISC-V Summit China is currently being planned for August 2023.
RISC-V Summit Europe 2023
Jun 05, 2023 | Barcelona, Spain
The RISC-V Summit Europe will be the premier event that connects the European movers and shakers - from industry, government, research, academia and ecosystem support - that are building the future of innovation on RISC-V.
Interview with Semidynamics at IP SoC SV 23
May 29, 2023 | IP SoC SV 23
At D&R IP SoC Silicon Valley 23 with Roger Espasa, CEO at Semidynamics Technology Services.
SemIsrael Tech Webinar: RISC-V Out-of-order IP Core and Vector Unit by Roger Espasa, CEO & Founder of Semidynamics
May 02, 2023 | SemIsrael Tech Webinar
You can now watch the presentation and live Q&A that our CEO Roger Espasa did in SemIsrael Tech Webinar on May 2nd 2023
Semidynamics will participate at The SupercomputingAsia (SCA2023)
Feb 27, 2023 | The SupercomputingAsia (SCA2023)
Semidynamics participated at SCA2023- Supercomputing Asia, 27 February - 2 March, 2023. Thank you for your participation in our event. We appreciate having you in attendance and look forward to working with you.
Semidynamics at HiPEAC 2023 Conference
Jan 16, 2023 | HiPEAC 2023 Conference
Roger Espasa talked on the panel session: European RISC-V in HPC prospective.
Roger Espasa, Semidynamics' CEO, participated at Open Source Workshops for Computing & Sustainability
Dec 02, 2022 | Open Source Workshops for Computing & Sustainability
Roger Espasa participated in the session that discussed the threats and opportunities associated with the aforementioned expansion at the processor level, as well as the strengths that Europe can count on and the weaknesses that must be overcome.
Roger Espasa, Semidynamics' CEO, participated at Workshop on competence centres in semiconductors
Nov 30, 2022 | Workshop on competence centres in semiconductors
Roger Espasa participated in the session: Stakeholders’ needs and expectations from European microelectronics competence centres network.
Semidynamics en las Jornadas SARTECO 2022
Sep 09, 2022 | SARTECO 2022
Semidynamics estuvo presente en las Jornadas SARTECO 2022. Del 21 al 23 septiembre, Alicante. Gracias a los participantes y organizadores del evento.
Roger Espasa, Semidynamics' CEO, participated at The RISC-V Summit China 2022
Aug 25, 2022 | RISC-V Summit China 2022
In this talk Roger Espasa presented the characteristics of Semidynamics' VPU (Vector Processor Unit) and its integration with Atrevido, Semidynamics' out-of-order RISC-V core supporting the RISC-V vector extension.
Semidynamics at HiPEAC 2022 Conference
Jun 17, 2022 | HiPEAC 2022 Conference at Budapest
Semidynamics had a booth in HiPEAC 2022 Conference at Budapest, June 20- 22, 2022.
We appreciate the interest shown in our company. Thank you for attending the event and making it successful.
We appreciate the interest shown in our company. Thank you for attending the event and making it successful.
Semidynamics participa en la 2a edición de las Jornadas de Fondos Europeos de Recuperación.
May 12, 2022 | 2a edición de las Jornadas de Fondos Europeos de Recuperación
Roger Espasa participa en la mesa: Tecnología de vanguardia: microchips, semiconductores y digitalización de pymes de la 2ª edición de las Jornadas de Fondos Europeos de Recuperación, organizada por elDiario.es.
Roger Espasa participated at the Spring 2022 RISC-V week with the talk "Atrevido: Semidynamics Out-of-Order RISC-V Core"
Apr 12, 2022 | Spring 2022 RISC-V week
In this talk Roger Espasa described Atrevido, Semidynamic's out-of-order RISC-V Application core supporting the RISC-V vector extension. He covered the pipeline basics, the interplay between the vector specification and out-of-order execution and he discussed the Gazzillion(TM) misses feature, specifically tailored to support HPC vector programs.
Roger Espasa participated at the RISC-V Summit with the talk "Implementation of an Out-of-order RISC-V Vector Unit"
Dec 06, 2021 | RISC-V Summit
In this talk Roger Espasa described Semidynamics' vector unit implementing the RVV-010 specification and he focused on the challenges of supporting out-of-order execution for vector instructions. He covered the challenges of renaming vector registers in the presence of LMUL, SEW, narrowing & widening and the different flavors of masking in the RV vector ISA. He also provided an overview of the vector load/store pipeline.
The RISC-V Summit - December 6-8, 2021 in San Francisco, CA.
The RISC-V Summit - December 6-8, 2021 in San Francisco, CA.
Alberto Moreno and Roger Espasa participated in the RISC-V Forum: Vector and Machine Learning with the talk "OVI: The Open Vector Interface"
Sep 15, 2021 | RISC-V Forum
In this talk, Alberto Moreno and Roger Espasa presented OVI, an open protocol to connect a RISC-V core with a loosely coupled vector unit compliant to the RISC-V vector specification. OVI has been used to connect the Avispado core from SemiDynamics to the Vitriuvius vector unit from the Barcelona Supercomputing Center. In this talk we covered the details of the protocol and explained how it can enable a quicker implementation of a RISC-V compliant vector unit with custom extensions.
Roger Espasa, Semidynamics' CEO, participated at the ACM Europe Summer School on HPC Computer Architectures for AI and Dedicated Applications
Aug 31, 2021 | ACM Europe Summer School on HPC Computer Architectures for AI and Dedicated Applications
In this talk, SemiDynamics discussed its family of high-bandwidth RISC-V application cores, targeted at application domains such as Machine Learning, Recommendation Systems, Sparse Computation, HPC and Key-Value Store. We described the open vector interface that allows connecting a RISC-V vector unit to SemiDynamics cores.
Roger Espasa, Semidynamics' CEO, participated at the first RISC-V World Conference in China 2021
Jun 22, 2021 | RISC-V World Conference in China 2021
In his talk, Roger Espasa presented SemiDynamics' family of high-bandwidth vector-capable RISC-V IP cores: the in-order core (Avispado) and the out-of-order core (Atrevido). He also covered the "gazzillion misses" technology capable of sustaining a high request rate to memory and introduced Semidynamics' RISC-V Vector Processing Unit.
Roger Espasa, Semidynamics' CEO, participated at the 2nd RISC-V Week 2021
Mar 31, 2021 | 2nd RISC-V Week 2021
In his talk, Roger Espasa discussed SemiDynamics' family of high-bandwidth RISC-V application cores, targeted at application domains such as Machine Learning, Recommendation Systems, Sparse Computation, HPC and Key-Value Store. He covered the "gazzillion misses" technology capable of sustaining a high request rate to memory and described the in-order core (Avispado) and the out-of-order core (Atrevido). He also described the open vector interface that allows connecting a RISC-V vector unit to SemiDynamics cores.
Roger Espasa, Semidynamics' CEO, participated at the Third Annual RISC-V Summit
Dec 09, 2020 | Third Annual RISC-V Summit
Key Takeaways:
- Two new families of cores will be introduced: in-order and out-of-order
- Very high-bandwidth capable. Ideal for SoC/Domains where high bandwidth an low area is needed
- Open Vector Interface that will facilitate developing specialized vector units will be disclosed
Verification Challenges of an Exascale Supercomputer
Oct 28, 2020 | DVCon Europe
Roger Espasa participated in the Virtual Panel "Verification Challenges of an Exascale Supercomputer" at the 2020 Design and Verification Conference in Europe (DVCon Europe)
Roger Espasa, Semidynamics' CEO, announced a New Family of High Bandwidth Vector-Capable Cores at the RISC-V Global Forum
Sep 03, 2020 | Global Forum
Semidynamics discloses its new RISC-V application cores, targeted at bandwidth-hungry application domains such as Machine Learning, Recommendation Systems, Sparse Computation, HPC and Key-Value Stores. Semidynamics also open source its "Open Vector Interface (OVI)", a public spec that allows third-parties to design their own vector unit and connect it to Semidynamics cores.