a. Daring
b. Bold
c. Adventurous


64-bit Core
2/3/4-wide Out-Of-Order
Multiprocessor Ready
Direct hardware support for unaligned accesses
Register Renaming
(including V-regs)
MMU Linux Ready
Gazzillion Misses™
more info

Available extensions

Bit Manipulation
Open Vector interface
more info
Vector Unit
more info

Customisable options

Vector spec 1.0 (vector ready)
Branch Predictor
I$ from 8KB to 32KB
D$ from 8KB to 32KB

Atrevido pipeline

Customisable 2/3/4-wide Out-Of-Order
Atrevido pipeline


  • decodes/retires_2_instructions/cycle
  • Register Renaming
  • Including V-regs
  • Out-of-Order issue
  • Out-of-Order completion
  • Gazzillion Misses™
  • SV48
  • Direct hardware support for unaligned accesses


  • I$ from 8KB to 32KB
  • D$ from 8KB to 32KB
  • Branch Predictor

Target Markets

Machine Learning

The Atrevido core, with its Out-of-Order scheduling engine combined with our Gazzillion technology, can deal with highly sparse data, with long memory latencies and with high-bandwidth memory systems, typical of current machine learning applications.

Key-Value Stores

In-memory caching and key-value processing requires large numbers of outstanding transactions to your memory subsystem.

Our Gazzillion Misses™ technology is especially suited for these demands, allowing you to sustain full memory bandwidth with fewer processing cores.

Recommendation Systems

The Gazzillion technology is specifically designed for Recommendation Systems, a key part of DataCenter Machine Learning.

By supporting hundreds of misses per Atrevido, you can build an SoC that smoothly delivers highly sparse data to the computer engines without a large silicon investment.

Furthermore, the 2-way Out-of-Order core helps to accelerate the not-so-parallel portions of Recommendation Systems.

Sparse Data/HPC

Gromacs? Sparse Matrices? PDEs? OMP? MPI? Multi-level parallelism? You name it!

HPC has to deal with large, multi-dimensional, sparse data and support heterogeneous parallelism at multiple levels.

Atrevido, with Out-of-Order execution and Gazzillion Misses™ technology, is the right match for the HPC domain, be it Embedded HPC, Edge or DataCenter level.

64-bit Core

Ready for the most demanding workloads, Atrevido supports large memory capacities with its 64-bit native data path. With its complete MMU support, Atrevido is also Linux-ready, including multiprocessing.

Vector Ready

Atrevido supports the RISC-V Vector Specification 1.0 as well as SemiDynamics Open Vector Interface, giving you freedom of choice between your own custom Vector Unit and using Semidynamics offerings.

Vector Instructions densely encode lots of computations, thereby reducing energy per operation.

Vector Gather instructions support sparse tensor weights efficiently, helping machine learning workloads.

Multiprocessor Ready

Atrevido supports cache-coherent Multiprocessing environments. Its native CHI interface can be tailored down to AXI, depending on your needs.

Be it 2, 4, or hundreds of cores, Atrevido is ready for your next SOC.