Built into our fully customisable 64-bit RISC-V family cores and meant for memory intensive applications, Gazzillion Misses™ helps to avoid latency issues when accessing off-chip memory.
Traditional processors follow a "stop-and-go" mode of operation. The figure below shows three load instructions (violet color) flowing down a 6-stage pipeline. After the "A" stage (ALU/Address Generation) the loads experience a cache miss ("M", red box). The processor makes a request to memory and continues processing. However, on the next cache miss, four instructions later, the processor cannot issue more memory requests and, therefore, it has to wait for the data from the first miss to be returned from memory before proceeding. Effectively, the processor will be idle for about 400 clock cycles in the example below.
In contrast, Semidynamics Gazzillion™ technology allows the processor to send up to 128 requests to the memory system, whereas other cores can only tolerate very few cache misses. This means that the processor continues doing useful processing while previous misses are served. The figure below shows how up to 128 misses can be sent to the memory system before the processor stalls waiting for memory accesses to complete. In this case, the idle time is reduced to almost zero, because the stop happens very close to the time the first cache miss is resolved.
Comparison to Other Cores
To put the previous explanation in perspective, the figure below compares the Gazzillion technology in the Atrevido and Avispado cores to other popular cores available in the market.
In the figure, the horizontal axis represents the number of instructions retired/issued per cycle in each core, while the vertical axis shows the maximum number of outstanding misses that each core supports.
It can be seen that Atrevido and Avispado stand out from all other cores, whether RISC-V or not, with their ability to process up to 64 or 128 misses respectively.
With Gazzillion technology, your design can tolerate large memory latencies and sustain high-memory bandwidth. This translates into higher performance for your applications and a much easier task for your software team to write code for your platform.
Summarizing, the Gazzillion benefits are:
- Off-chip memory can be accessed at the same super speed as on-chip.
- Streams data at over 60 Bytes/cycle from memory.
- Improves performance.
- Reduces software complexity.
Our Gazzillion Misses™ technology is highly beneficial for Machine Learning, Recommendation systems, Key-value stores and Sparse Data/HPC. It is also a perfect fit for SoCs with limited SRAM/Cache, high-bandwidth/streaming and with vector units.
Ready for the CXL.mem Future!
Memory disaggregation is coming thanks to the industry adoption of the CXL.mem protocol. The implication for your next SoC design is that memory will be even further away from the cores inside your SoC. In other words, latency will greatly increase in the new era of disaggregated memory. Gazzillion is ready for this new era of high latency by providing you with highly efficient latency tolerance technology.