RISC-V Emulator Engineers

Are you passionate about the future of processor architecture and emulation technology? We are looking for you! 
As a RISC-V Emulator Maintenance and Upgrade Engineer at Semidynamics, you will play a crucial role in advancing our cutting-edge RISC-V cores. Your responsibilities will include maintaining and upgrading RISC-V emulators, ensuring seamless functionality with our proprietary hardware IPs. This is an exciting opportunity to work closely with both RTL and software teams, contributing to the ongoing development of our RISC-V cores.

AI Compiler Engineers

We are looking for candidates to staff our AI Compiler team. If you're passionate about compilers, performance, optimizations, and AI you'll find the right challenges with us. You’ll be working with RISC-V backend compilers to be plugged into the major AI software frameworks (Pytorch, ONNX, Etc.) to extract the maximum performance from our vector and tensor units.  You'll be working side by side with the RTL team, you'll get the ultimate detail on the microarchitecture and performance of your code, and will be able to influence the underlying design to maximize AI throughput on RISC-V.

Compiler Engineers

We are looking for candidates to staff our Compiler team. If you're passionate about compilers, performance, and optimizations, you'll find the right challenges with us. We want to optimize the main C compilers (GCC & Clang) for our Gazzillion(tm)-enabled Atrevido core and its vector unit. You'll be working side by side with the RTL team, you'll get the ultimate detail on the microarchitecture and performance of your code, and will be able to influence the underlying design to maximize throughput on RISC-V.

SDK Engineers

We are looking for candidates to staff our Software team. If you’re passionate about profiling, performance, emulation, software distribution, IDEs, and packaging, you'll find the right challenges with us. We want to enhance our software platform to provide a turnkey solution to our customers, which enables them to easily start developing software with our optimized libraries and APIs. You’ll be working side by side with our Compilers and AI teams, and will be able to influence the development of our software stack. 

AI Software Engineers

We are looking for candidates to staff our AI compiler and library teams. If you're passionate about AI, machine learning, algorithms, compilers, performance, and optimizations you'll find the right challenges with us. We want to port the key AI execution frameworks to the RISC-V vector architecture and optimize them for our Gazzillion(tm)-enabled Atrevido core. You'll be working side by side with the RTL team, you'll get the ultimate detail on the performance of your code and will be able to influence the underlying design to maximize the  AI throughput on RISC-V.

 

CXL/PCIe Architects

We're looking for a strong candidate with expertise in PCIe and CXL2.0/3.0 to architect and design our CXL-to-CHI bridge. Our cores use the AMBA-CHI protocol for coherency and we want the CXL.mem and CXL.cache protocols to allow our IP to seamlessly interoprate with CXL-enabled hosts. You will be architecting the bridge and also writing the RTL for it, so RTL skills are also required!

Back-End Engineers

We have multiple open position in our back end team and we're looking for individuals with experience in synthesis, place & route flows and floorplaning and wireplanning. Experience in clock tree synthesis and/or custom clock trees is also very welcome. Experience in netlist power analysis tools (such as PrimeTime/PX) will also be key in these positions. You'll be helping in floorplanning in a very advanced technology node, creating the synthesis and place & route flow, integrating several custom blocks and running the resulting p&r netlists though power analysis tools.

PCie Device Driver Engineers

We're looking for driver engineers with a proven track record of bringing up a PCIe driver for the Windows and Linux environments.

Verification Engineers

We have multiple open positions in our verification team and we're looking for individuals with either a strong Verification or strong microarchitecture background interested in working in the verification of a RISC-V design for an advanced technology node. Areas of focus are the vector instructions, the RISC-V base ISA, the RISC-V privileged ISA, cache coherency protocols, inter-processor communication protocols and full SoC verification.