Role Overview

We are looking for an experienced STA & Synthesis Lead Engineer with hands-on experience in Logic synthesis, static timing analysis, timing closure, and design optimization. The ideal candidate will have strong expertise in PPA optimization, MMMC timing analysis, SDC constraints, ECO implementation, and formal equivalence checking, with the ability to work closely with RTL, DFT, and Physical Design teams.The candidate will be responsible for driving synthesis and timing sign-off activities from RTL through implementation, identifying timing bottlenecks, and delivering optimized designs that meet Power, Performance, and Area (PPA) targets.

Key Responsibilities

1. Logic Synthesis & PPA Optimization
● Perform physical-aware RTL-to-gate synthesis for complex digital designs.
● Optimize synthesis results for Power, Performance, and Area (PPA) targets.
● Analyze synthesis reports and identify opportunities for timing, area, and power
improvements.
● Work with RTL designers to resolve synthesis-related issues and improve RTL quality.
● Support synthesis flows across block-level and top-level designs.

2. Constraint Development & Management
● Develop, review, validate, and debug SDC timing constraints for block-level and top-level
designs.
● Define and maintain constraints for functional, scan, and DFT modes.
● Handle clock definitions, generated clocks, clock relationships, I/O constraints, false paths,
multicycle paths, and case analysis.
● Debug constraint-related timing issues and ensure constraint completeness and
correctness.

3. Static Timing Analysis & Sign-Off
● Perform Static Timing Analysis (STA) across Multi-Corner Multi-Mode (MMMC) scenarios.
● Drive timing sign-off for setup, hold, recovery, removal, and clock-gating checks.
● Analyze critical paths, timing violations, clock interactions, and design bottlenecks.
● Understand and account for clock skew, jitter, latency, uncertainty, and variation effects.
● Perform timing analysis across functional and DFT/scan modes.
● Support and debug CDC-related timing issues in collaboration with RTL/CDC teams.
● Technical understanding of PVT conditions and their application in timing analysis.

4. Timing Closure & ECO
● Identify critical timing paths and develop effective strategies for timing closure.
● Generate, implement, and validate timing and functional ECOs.
● Analyze the impact of ECOs on timing, area, power, and functionality.
● Work closely with Physical Design/P&R teams to resolve post-placement and post-route
timing issues.
● Support iterative synthesis, implementation, and timing optimization until sign-off.

Technical Skills
● 7+ years of hands-on experience in synthesis and STA.
● Deep understanding of timing concepts.
● Strong knowledge of MMMC timing analysis and sign-off methodologies.
● Experience with SDC constraint development and debugging.

Tools and Methodologies
● Fusion compiler, Primetime, primetime constraints checker, formality, VCLP.
● Physical synthesis and STA flow in 3nm and below tech nodes.
● Timing analysis - zero wireload and with parasitic or SDF backannotation.

Why Semidynamics?

• Work at one of Europe’s most promising deep-tech semiconductor start up - from silicon to systems - Semidynamics.
• Accelerated development path.
• 4 days per week in the Barcelona office (city center), 1 day WFH.
• 1 week of work from everywhere in the world.
• Competitive package.
• A collaborative, technical, and growth-oriented environment that values direct ownership and clear thinking.