Name: Semidynamics Videos
Brand: Semidynamics

Jun 16, 2026 YouTube

【2026 RISC-V Taipei Day】Semidynamics: Miquel Izquierdo

Scaling AI Workloads with Semidynamics RISC-V Cores Miquel Izquierdo | VP of Engineering, Semidynamics As VP of Hardware, Miquel Izquierdo is instrumental in leading the end-to-end development life cycle of Semidynamics’ AI systems. From initial architecture to final rack testing, he provides the strategic direction necessary to integrate silicon design, verification, and advanced packaging into a cohesive hardware platform. Miquel serves as a key driver of PPA (Power, Performance, and Area) optimization, ensuring the company’s systems set new industry benchmarks for commercial excellence and global scalability. Miquel brings deep expertise in performance optimization and system architecture, with a career defined by extracting maximum efficiency from high-density compute environments. He is a specialist in advanced networking, having architected mission-critical interconnect fabrics both on-chip and at the rack-to-rack level. He holds degrees in Computer Engineering and Electronics, complemented by a Master’s in Electrical Engineering and Computer Science from the University of California. At Semidynamics, his mission is to deliver a transformative hardware platform that provides the massive computational capacity required for the full realization of large-scale AI. 👉 Subscribe for more content from RISC-V Taiwan Alliance https://www.twiota.org/RISC-V #RISCV #RISCVTaipeiDay #AIInference #OpenHardware #COMPUTEX2026 #TechForum #RVTA

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Mar 19, 2026 YouTube

Roger Espasa | Workshop 1 | Regime 28 & Europe’s Innovation Future

At FOROINNOVAEMPRENDE (AEMETIC), our CEO, Roger Espasa, explores how Europe can turn its talent and knowledge into real innovation and global tech leadership.

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Mar 19, 2026 YouTube

José Manuel Leceta | Workshop 1 | Regime 28 & Europe’s Innovation Future

At FOROINNOVAEMPRENDE (AEMETIC), our VP Public Policy, José Manuel Leceta, explores how Europe can turn its talent and knowledge into real innovation and global tech leadership.

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Mar 18, 2026 YouTube

Semidynamics @ Embedded World 2026 | CSO Interview

At Embedded World 2026, our CSO Volker Politz, shares insights into Semidynamics’ technology, our approach to innovation, and how we tackle advanced memory handling challenges. Discover how we are shaping the future of high-performance computing.

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Mar 11, 2026 YouTube

Semidynamics at embedded world 2026

Semidynamics joined RISC-V International as a co-exhibtor at embedded world 2026. About: Founded in Barcelona in 2016, Semidynamics designs European processor technology for the AI age—built on the open RISC-V standard AI isn’t just “more FLOPS.” It’s moving and processing data efficiently. Our customizable AI enabled CPU feeds models faster and uses energy smarter Semidynamics cuts memory bottlenecks so workloads run smoothly instead of waiting for data Learn More: https://semidynamics.com/ #riscv #embeddedworld #semidynamics #shorts

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Mar 05, 2026 YouTube

🎙️Semidynamics - Roger Espasa at MWC26

Entrevista a Roger Espasa, CEO y fundador de Semidynamics, una de las 49 empresas presentes en #SpainMWC26, donde nos ofrece una visión en profundidad sobre la compañía.

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Mar 04, 2026 YouTube

The chip moment

Our CEO, Roger Espasa, joins a panel discussion on the strategic importance of semiconductors and high performance accelerators for Europe’s technological sovereignty, highlighting how efficient, specialized chips for AI and Edge Computing are key to reducing costs, lowering energy consumption, and decreasing external dependency.

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Jun 12, 2025 YouTube

What Makes RISC-V Perfect for AI? SemiDynamics Explains

• The latest disruptive technology, ready to evaluate for your next design: https://ipxchange.tech/ • Join the ipX community: https://ipxchange.tech/sign-up/ • Submit your own electronics projects: https://ipxchange.tech/projects/ • Follow us on LinkedIn: https://www.linkedin.com/company/ipxchangeltd/ Learn more about ipXchange here: https://ipxchange.tech/about/ Discover how SemiDynamics is reshaping the world of AI chip design with its revolutionary approach to RISC-V-based AI solutions. In this exclusive PCIM 2025 interview, we dive deep into how RISC-V architecture offers unprecedented freedom, customisability, and scalability for building cutting-edge AI hardware and NPU systems. If you’re a design engineer working on next-gen silicon, interested in AI processors, machine learning at the edge, or RISC-V instruction set extensions, this is the video for you. We explore how SemiDynamics’ SurferV platform merges vector and tensor units into a single RISC-V-based NPU IP block, enabling AI compute performance from 1 TOPS to hundreds of TOPS, tailored to your needs. 🔍 Key topics covered: – Why RISC-V for AI is the future – Custom instructions for AI acceleration – How SemiDynamics supports full-stack AI SoC development – The role of open ISA in deep learning workloads – Scalable NPU design for inference and training – Integrating RISC-V with vector and tensor compute – Support for models like Llama and edge inference optimisation – Custom silicon design with licensable IP – Why engineers are moving away from closed ARM & x86 systems – How RISC-V enables freedom to innovate in AI hardware ✅ Targeted keywords: RISC-V, SemiDynamics, AI chip, NPU, neural processing unit, AI accelerator, RISC-V AI processor, RISC-V NPU, AI silicon, RISC-V IP, custom chip design, scalable NPU, vector processor, tensor processor, RISC-V vs ARM, machine learning hardware, deep learning IP, AI inference chip, SoC AI integration, RISC-V for AI, open source CPU, edge AI RISC-V, embedded AI 💡 Whether you’re targeting AI for data centres, consumer electronics, or automotive edge AI, SemiDynamics has a ready-made RISC-V NPU platform with software-defined control, total transparency, and the ability to extend or customise the instruction set. 👉 Like, comment, and subscribe for more AI hardware interviews, chip design insights, and deep dives into RISC-V-based compute platforms! #RISC-V #AIChip #SemiDynamics #NPU #SoCDesign #OpenHardware #PCIM2025 #ipXchange

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Apr 08, 2025 YouTube

Executing LLM inference in Semidynamics' All-In-One - Pedro Marcuello, Semidynamics

Our IP Director, Pedro Marcuello, presents our All-In-One solution during Embedded World 2025 show in Nuremberg

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Apr 08, 2025 YouTube

Interview with Semidynamics at embedded world 2025

RISC-V International interviews our CSO Volker Politz during the Embedded World 2025 show in Nuremberg

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Apr 08, 2025 YouTube

Semidynamics Aliado in the inference ecosystem - Jordi Vaquero, Semidynamics

Our Software team lead presents our Aliado SDK solution during the Embedded World 2025 show in Nuremberg

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Feb 13, 2025 YouTube

'The Electronics Reporter' Stuart Cording interviews Semidynamics' Roger Espasa and Volker Politz

Drawing upon the open RISC-V instruction set architecture (ISA), Semidynamics is able to offer custom silicon providing innovative, efficient solutions to unique customer problems. In this interview, Stuart Cording asks Semidynamics' Roger Espasa and Volker Politz to find out how they tackle the memory wall and provide high-bandwith, high-tensor, high-vector performance. Further information: Semidynamics: https://semidynamics.com HiPEAC 2025: https://www.hipeac.net/2025/barcelona/#/ Stuart Cording: https://www.cordingconsulting.com/

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Jan 16, 2025 YouTube

Semidynamics Designs Customizable RISC-V Technology for the Next Five AI Revolutions with Cadence

It takes about three years to design a chip. At the same time, there’s a revolution in AI happening every six months. By the time the chip has been designed, five AI revolutions have taken place. Five AI revolutions from now, will your technology remain useful? Semidynamics answers yes. Learn how Semidynamics leveraged Cadence’s Xcelium Logic Simulator and Jasper Formal Verification Platform to provide fully programmable, customizable RISC-V technology with a vector unit, an out-of-order unit, and a tensor unit, all in one. Connect with Cadence: Website: https://www.cadence.com Free Trials: https://www.cadence.com/en_US/home/tools/free-trials.html YouTube: https://www.youtube.com/channel/UC5qqAsDzbA0zAQNBBQVsS0Q Facebook: https://www.facebook.com/CadenceDesign LinkedIn: https://www.linkedin.com/company/cadence-design-systems/ Twitter: https://twitter.com/Cadence About Cadence: Cadence is a pivotal leader in electronic systems design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design™ strategy to deliver software, hardware and IP that turn design concepts into reality. Cadence® customers are the world’s most innovative companies, delivering extraordinary products from chips to boards to complete systems for the most dynamic market applications, including hyperscale computing, 5G communications, automotive, mobile, aerospace, consumer, industrial and healthcare. For nine years in a row, Fortune magazine has named Cadence one of the 100 Best Companies to Work For. Learn more at https://www.cadence.com.

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Oct 31, 2024 YouTube

Demo: Running Transformers on Semidynamic's "All-In-One" Vector and Tensor Unit

Demo: Running Transformers on Semidynamic's "All-In-One" Vector and Tensor Unit - Roger Espasa, Semidynamics In this talk we will cover the latest developments in running modern transformers , such as LLama-2, on Semidynamics RISC-V "All-In-One" solution, comprising a core, a Vector Unit and a Tensor Unit. In this talk you'll learn about how ONNX RT is used to deploy modern models on Semidynamics solution, on how the ratio of the vector to tensor compute is important for balanced execution and how the all-in-one can be scaled-out to reach different performance levels.

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Oct 14, 2024 YouTube

The role of RISC-V in the European Processor Initiative - eeNews Interview with Roger Espasa

The role of RISC-V in the European Processor Initiative The European Processor Initiative aims to bring together research, design and manufacturing of a how-grown European processor. The initiative is well underway. The first processors have been delivered and the next generation is getting ready to be used in Europe’s second exascale computer, which is due to come online in 2026. Also part of the program is EPAC, even accelerator chip based on the RISC-V ISA. This technology is my focus in this interview with Roger Espasa, CEO and founder at Semidynamics Technology Services in Barcelona.

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Jul 05, 2024 YouTube

Conversation with Calista Redmond, RISC-V CEO, about Semidynamics All-in-One AI solution

At RISC-V Summit Europe 2024, Calista Redmond, CEO of RISC-V, interviews Roger Espasa, CEO of Semidynamics, on their new All-in-One AI solution. Espasa explains how this unified RISC-V platform simplifies software, boosts customization, and is ready for future AI advancements.

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Jul 05, 2024 YouTube

All-in-One RISC-V AI compute engine - Semidynamics at RISC-V Summit Europe

In this talk we will describe Semidynamics' solution for future-proof AI compute, based on the combination in a single element of Semidynamics RISC-V core, vector and tensor unit. We will cover the new tensor instructions implemented by Semidynamics, how these can be used in AI convolutions and matrix multiplication. We will also cover the need for the vector unit in modern AI models, such as LLMs, to properly run activations.

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Jul 05, 2024 YouTube

Demo: Boosting AI on Semidynamics RISC-V Cores with Custom Tensor Instructions

Demo Theatre Talk at RISC-V Summit Europe 2024. In this talk, we will present Semidynamics custom tensor instructions and we will show how to use them to accelerate machine learning workloads. Furthermore, we will also show the speedups achieved on real deep learning models when using the new tensor instructions.

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Jun 26, 2024 YouTube

Semidynamics Vector Unit Performance Demonstration: Scalar vs. Vector Instructions

In this demo session, we showcase the Semidynamics Vector Unit running several visual benchmarks (right) and compare their performance against a core without a Vector Unit (left). Witness the significant performance boost as we demonstrate the difference between scalar and vector instructions, with vector instructions achieving up to ~3x speedup.

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Jun 25, 2024 YouTube

Semidynamics' All-in-One RISC-V AI Compute Engine: Highlights from the RISC-V Summit in Munich

In this talk, Roger Espasa will describe Semidynamic’s solution for future-proof AI compute, based on the combination in a single element of Semidynamics' RISC-V core, vector, and tensor unit. Jon will cover the new tensor instructions implemented by Semidynamics, how these can be used in AI convolutions and matrix multiplication. He will also discuss the importance of the vector unit in modern AI models, such as LLMs, to properly run activations.

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May 03, 2024 YouTube

Boosting AI on Semidynamics RISC-V Cores with Custom Tensor Instructions - Embedded World 2024

Semidynamics presents its all-in-one RISC-V AI Compute solution, featuring a simplified architecture that integrates RISC-V cores, vector units, and tensor units. This design streamlines programming, reduces latency, and enhances performance for AI applications. Additionally, it offers customizable options to address a wide range of requirements.

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Dec 03, 2023 YouTube

Demo: Boosting AI on Semidynamics RISC-V Cores with Custom Tensor Instructions - RISC-V Summit NA 2023

Demo: Boosting AI on Semidynamics RISC-V Cores with Custom Tensor Instructions - José María Arnau, Semidynamics The presentation will show how the RISC-V Vector ISA can be extended with custom Tensor Instructions. Furthermore, we will show how machine learning workloads can be modified to use the Tensor Instructions. Finally, the talk will present an analysis of performance, showing the speedups achieved by popular deep learning models when using the new instructions.

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Nov 29, 2023 YouTube

Boosting AI on Semidynamics RISC-V Cores with Custom Tensor Instructions - RISC-V Summit NA 2023

Boosting AI on Semidynamics RISC-V Cores with Custom Tensor Instructions - Roger Espasa & José María Arnau, Semidynamics This talk will present the new Tensor Instructions developed at Semidynamics. The first key insight will be how to extend the RISC-V ISA to accommodate Tensor Instructions for Artificial Intelligence (AI) and Machine Learning (ML). These instructions are built on top of the RISC-V Vector Extension and use the vector register file for holding tensors. The second insight from this talk will be how to use the new Tensor Instructions to accelerate essential kernels in AI/ML, such as convolutions or fully-connected layers. We will show how popular ML models can leverage the new instructions to achieve significant speedups. Performance results from a real implementation will also be included in the presentation. At Semidynamics we developed a Vector Processing Unit (VPU) fully compliant with the RISC-V Vector Extension 1.0, and we implemented the Tensor Instructions in our VPU. We are looking forward to sharing our experience and results with the RISC-V community.

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Nov 23, 2023 YouTube

Overview of Semidynamics RISC-V AI Solutions | 2023 SEDEX 현장인터뷰

In this video, the CEO of Semidynamics provides an overview of the company, discussing their focus on RISC-V IP production. Learn about their in-order and out-of-order CPU offerings, their emphasis on high memory bandwidth, and their vision for integrating RISC-V technology into devices across various industries.

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Jul 05, 2023 YouTube

Semidynamics Highly Configurable OOO Vector Unit - RISC-V Europe Summit 2023

In this engaging presentation, Roger Espasa, the founder and CEO of Semidynamics, introduces their innovative out-of-order Vector Processing Unit designed for RISC-V architecture. He discusses the unique features of their highly configurable Vector Unit, emphasizing its ease of programming compared to traditional GPUs and its potential for high performance in parallel computing. The talk covers the customizable aspects of the Vector Unit, including the number of cores and data types, along with advanced technologies that enhance performance, such as out-of-order execution and a seamless connection to the memory system. Roger highlights the applications of their technology in machine learning, HPC, and data-intensive processes, and invites attendees to visit their booth for demonstrations and further insights.

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Jun 28, 2023 YouTube

Conversation with Calista Redmond, RISC-V CEO, about the new Semidynamic Vector Unit and its role in accelerating processor performance for HPC and AI applications

Calista Redmond, CEO of RISC-V International, joins Roger Espasa, Founder and CEO of Semidynamics, to discuss their new vector unit, making processors go fast in HPC and AI applications, and plans for the future.

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Jun 28, 2023 YouTube

Semidynamics Vector Unit Performance Demonstration - RISC-V Europe Summit 2023

Semidynamics Vector Unit Performance Demonstration Roger Espasa, CEO and Founder, Semidynamics Abstract In this demo session we will show the Semidynamics vector unit running several visual benchmarks and compare their performance against a core without vector unit.

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Jun 25, 2023 YouTube

Tailor Made RISC-V Performance - eeNews interview with Roger Espasa/Semidynamics

The RISC-V Instruction Set Architecture is perfectly suitable for fine tuning the performance depending on the applications. In this interview Roger Espasa, CEO and Founder at Semidynamics Technology Services explains how cores and vectorizing can be used to build client specific silicon. We also hear more about the process of development, lead times and the background of the company. Production eeNews Europe / Wisse Hettinga

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Jun 06, 2023 YouTube

Doom vectorized for RISC-V! Watch speedup when run on Semidynamics vector unit with 8 vector cores!

Doom game demo comparison using Semidynamics Atrevido 423 core running with and without Semidynamics vector unit (8 vector cores). Right hand screen with the Vector Unit enabled.

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May 15, 2023 YouTube

Semidynamic's RISC-V OOO IP Core and Vector Unit

In this contribution we will describe Semidynamic's RISC-V IP comprising its advanced family of out-of-order cores (code named Atrevido) and the companion out-of-order vector unit, fully compliant to the RISC-V 1.0 specification. The core and vector unit contain the Gazzillion(tm) misses technology, which make them ideal for environments with high memory latency and/or high bandwidth demands, such as CXL memory systems or HBM memory systems.

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Dec 13, 2021 YouTube

Implementation of Semidynamics OOO RISC-V Vector Unit - RISC-V Summit

Implementation of an Out-of-order RISC-V Vector Unit - Roger Espasa, SemiDynamics Technology Services In this talk we will describe Semidynamics' vector unit implementing the RVV-010 specification and we will focus on the challenges of supporting out-of-order execution for vector instructions. We will cover the challenges of renaming vector registers in the presence of LMUL, SEW, narrowing & widening and the different flavors of masking in the RV vector ISA. We will also provide an overview of the vector load/store pipeline. For more info about RISC-V, a free and open ISA enabling a new era of processor innovation through open standard collaboration, see: https://riscv.org/

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Sep 20, 2021 YouTube

OVI: The Open Vector Interface - Semidynamics - RISC-V Forums

OVI: The Open Vector Interface - Roger Espasa & Alberto Moreno, SemiDynamics OVI is an open protocol to connect a RISC-V core with a loosely coupled vector unit compliant to the RISC-V vector specification. OVI has been used to connect the Avispado core from SemiDynamics to the Vitriuvius vector unit from the Barcelona Supercomputing Center. In this talk we will cover the details of the protocol and explain how it can enable a quicker implementation of a RISC-V compliant vector unit with custom extensions. For more info about RISC-V, a free and open ISA enabling a new era of processor innovation through open standard collaboration, see: https://riscv.org/

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Sep 16, 2021 YouTube

Avispado: Semidynamics RISC-V core supporting the RISC-V vector instruction

In this talk, Semidynamics will discuss its family of high-bandwidth RISC-V application cores, targeted at application domains such as Machine Learning, Recommendation Systems, Sparse Computation, HPC and Key-Value Store. We will describe the open vector interface that allows connecting a risc-v vector unit to SemiDynamics cores.

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Mar 12, 2021 YouTube

DVCon Europe 2020 Panel: Verification Challenges of an Exascale Supercomputer

In this panel session of the DVCon Europe 2020, experts from various organizations discussed verification challenges. The panel was chaired by Tran Nguyen (Arm), moderated by Jean-Marie Brunet (Mentor, A Siemens Business), and with panelists: Mark Glasser (Cerebras) Gajinder Panesar (Mentor, A Siemens Business) Nasr Ullah (SiFive) and EPI partners Christian Beckmann (Atos) Ying-Chih Yang (SiPeral) Roger Espasa (SemiDynamics)

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Mar 11, 2021 YouTube

Semidynamics new family of High Bandwidth Vector-capable Cores

RISC-V Summit 2020 presentation by Roger Espasa

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Sep 08, 2020 YouTube

Semidynamics New Family of High Bandwidth Vector-Capable Cores - SemiDynamics

Semidynamics New Family of High Bandwidth Vector-Capable Cores - Roger Espasa, SemiDynamics In this session, SemiDynamics will disclose its new RISC-V application cores, targeted at bandwidth-hungry application domains such as Machine Learning, Recommendation Systems, Sparse Computation, HPC and Key-Value Stores. SemiDynamics will also open source its "Open Vector Interface (OVI)", a public spec that allows third-parties to design their own vector unit and connect it to SemiDynamics cores.

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Videos & Presentations

【2026 RISC-V Taipei Day】Semidynamics: Miquel Izquierdo

Roger Espasa | Workshop 1 | Regime 28 & Europe’s Innovation Future

José Manuel Leceta | Workshop 1 | Regime 28 & Europe’s Innovation Future

Semidynamics @ Embedded World 2026 | CSO Interview

Semidynamics at embedded world 2026

🎙️Semidynamics - Roger Espasa at MWC26

The chip moment

What Makes RISC-V Perfect for AI? SemiDynamics Explains

Executing LLM inference in Semidynamics' All-In-One - Pedro Marcuello, Semidynamics

Interview with Semidynamics at embedded world 2025

Semidynamics Aliado in the inference ecosystem - Jordi Vaquero, Semidynamics

'The Electronics Reporter' Stuart Cording interviews Semidynamics' Roger Espasa and Volker Politz

Semidynamics Designs Customizable RISC-V Technology for the Next Five AI Revolutions with Cadence

Demo: Running Transformers on Semidynamic's "All-In-One" Vector and Tensor Unit

The role of RISC-V in the European Processor Initiative - eeNews Interview with Roger Espasa

Conversation with Calista Redmond, RISC-V CEO, about Semidynamics All-in-One AI solution

All-in-One RISC-V AI compute engine - Semidynamics at RISC-V Summit Europe

Demo: Boosting AI on Semidynamics RISC-V Cores with Custom Tensor Instructions

Semidynamics Vector Unit Performance Demonstration: Scalar vs. Vector Instructions

Semidynamics' All-in-One RISC-V AI Compute Engine: Highlights from the RISC-V Summit in Munich

Boosting AI on Semidynamics RISC-V Cores with Custom Tensor Instructions - Embedded World 2024

Demo: Boosting AI on Semidynamics RISC-V Cores with Custom Tensor Instructions - RISC-V Summit NA 2023

Boosting AI on Semidynamics RISC-V Cores with Custom Tensor Instructions - RISC-V Summit NA 2023

Overview of Semidynamics RISC-V AI Solutions | 2023 SEDEX 현장인터뷰

Semidynamics Highly Configurable OOO Vector Unit - RISC-V Europe Summit 2023

Conversation with Calista Redmond, RISC-V CEO, about the new Semidynamic Vector Unit and its role in accelerating processor performance for HPC and AI applications

Semidynamics Vector Unit Performance Demonstration - RISC-V Europe Summit 2023

Tailor Made RISC-V Performance - eeNews interview with Roger Espasa/Semidynamics

Doom vectorized for RISC-V! Watch speedup when run on Semidynamics vector unit with 8 vector cores!

Semidynamic's RISC-V OOO IP Core and Vector Unit

Implementation of Semidynamics OOO RISC-V Vector Unit - RISC-V Summit

OVI: The Open Vector Interface - Semidynamics - RISC-V Forums

Avispado: Semidynamics RISC-V core supporting the RISC-V vector instruction

DVCon Europe 2020 Panel: Verification Challenges of an Exascale Supercomputer

Semidynamics new family of High Bandwidth Vector-capable Cores

Semidynamics New Family of High Bandwidth Vector-Capable Cores - SemiDynamics

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