Event
Roger Espasa participated at the Spring 2022 RISC-V week with the talk "Atrevido: Semidynamics Out-of-Order RISC-V Core"
Apr 12th, 2022
| Spring 2022 RISC-V week
In this talk Roger Espasa described Atrevido, Semidynamic's out-of-order RISC-V Application core supporting the RISC-V vector extension. He covered the pipeline basics, the interplay between the vector specification and out-of-order execution and he discussed the Gazzillion(TM) misses feature, specifically tailored to support HPC vector programs.