Foundation of the company
Chips are ubiquitous nowadays. Not only in your traditional computers, such as laptops and desktops. Not only inside the mobile devices that you carry, such as smartphones or tablets. They are present in your house: in your fridge, microwave or vacuum cleaner robot. They are in your city: in security cameras, controlling street lights or monitoring air pollution. They are in your car, providing assistance to the driver or even driving the vehicle. You wear them in your smartwatch or in your Bluetooth headphones. As we live in a digital world, our society depends on chips for work, entertainment, healthcare or security among many other areas.
But what is a chip? Simply put, a chip, a.k.a. processor or microprocessor, is the hardware that runs all the fancy applications that you use on a daily basis. More technically, it is a small flat piece of silicon that contains a digital circuit. The chip is the brain of the computer, as it orchestrates the behaviour of the whole digital system. A microprocessor performs computations, provides memory to store your data and controls the peripheral devices connected to it. State-of-the-art chips perform billions of calculations per second, providing unprecedented capability to process large amounts of data.
Roger Espasa founded Semidynamics back in 2016 with one key ambition: to develop efficient and reliable chips. Roger gathered a team of engineers with more than ten years of experience in the semiconductor industry. But how do a bunch of hardware engineers gather to create a new company? And in Europe, of all places?
The key factor was the appearance of the RISC-V [1] architecture in 2015. A computer architecture is a detailed specification of what the computer can do. Before 2015, there were mainly two architectures: x86 (Intel) and ARM. The x86 architecture dominated desktops and servers, whereas the ARM architecture was prevalent in mobile devices. Both of them were proprietary architectures, so any company that wanted to build a microprocessor had to pay an outrageous amount of money for a license. This was a main stopper for many start-up companies, resulting in a semiconductor industry with very few players. RISC-V changed this scenario by providing an open, clean and technically sound computer architecture that can be freely used at no cost. Not surprisingly, several start-ups were created with the ambition of making RISC-V chips. One of these new companies, Esperanto Technologies, became Semidynamics’ first client.
First years - Design Services for Esperanto
In January 2017 Semidynamics opened its office with only eight employees. It was located in Les Corts, an emblematic district of Barcelona, at five minutes walking from Barça’s football stadium. The office was small but cosy, and the team was eager to face the first challenge: designing a chip for Esperanto Technologies, a US company that wanted to build RISC-V processors for Artificial Intelligence (AI). Since AI applications exhibit high degrees of parallelism, our engineers designed a chip for Esperanto with 1024 RISC-V cores, called Minions. A core is a processing unit inside a chip that reads and executes program instructions. In the past, a processor had only one core. However, due to advances in manufacturing technology, nowadays it is possible to pack multiple cores within a single chip to improve performance, i.e. current microprocessors are multi-core.
In order to achieve high performance for AI applications, Semidynamics decided to provide each Minion core with a Vector Processing Unit (VPU) [3]. A VPU is a processing unit that works on a one-dimensional array of data elements, a. k. a. vector. Whereas conventional processors work on one element at a time, a VPU can process multiple elements at once, resulting in higher performance. A VPU exploits a form of parallelism called SIMD (Single-Instruction Multiple-Data), that is highly effective for applications that work on vectors. Such applications are very common in areas like scientific computing, engineering, artificial intelligence or data science among others. The main issue was that RISC-V did not include vector instructions by that time, so Semidynamics’ engineers had to define a custom vector extension for Esperanto.
During the first two years, 2017 and 2018, Semidynamics completed the architecture of the 1024-core chip and the specification of the custom vector instructions. Furthermore, the Minion cores were developed and validated, including the VPU. After completing the project for Esperanto, the company was ready for the next challenge.
Creating a portfolio of European RISC-V IPs
In 2017 and 2018, the EU was having internal talks to create an initiative to develop European chips, with the aim of reducing the technological dependency from foreign countries. These talks crystalised in the European Processor Initiative (EPI) [2], launched in March 2019.
Semidynamics helped shape EPI and was a founding participant in the initiative. Consequently, in 2019 the company started the development of a RISC-V core for the EPAC chip as part of the EPI SGA1 project, which had to necessarily be completely different from the technology developed for Esperanto. We chose Avispado as the name for this new core. Avispado is an in-order core, which means it executes the instructions in the same order they appear in the program. This simplifies the hardware, resulting in smaller size and lower energy consumption. Furthermore, Avispado was designed to be easily integrated with a VPU. With the aim of promoting interoperability between cores and VPUs, Semidynamics developed the Open Vector Interface (OVI) [4]. OVI is a technical specification that describes the interface between a core and a VPU. Avispado implements the OVI interface, so it can talk to any OVI-ready VPU developed by third parties. OVI was publicly released in September 2020.
One challenge when including a vector unit is to be able to constantly feed large amounts of data to the VPU. To this end, Semidynamics developed the Gazillion MissesTM technology, which is implemented in our Avispado core. This technology is able to effectively hide the latency of the off-chip main memory with low cost in area. Simply speaking, the Avispado core with Gazillion MissesTM is able to generate many memory requests in parallel to maximize memory bandwidth usage.
It took two years, 2019 and 2020, to create Avispado. This core was included in the EPAC chip [5] and manufactured in 2021. More specifically, the EPAC chip includes four Avispado cores at a frequency of 1.4 GHz. The bring-up was successful and Avispado executed the first programs on real silicon.
In 2021, Semidynamics was ready for the next challenge: to develop a larger core for the EUPilot project [6]. This core, named Atrevido, supports out-of-order execution: in case an instruction is stalled due to some long latency operation, an out-of-order core can inspect the next instructions in the program and execute younger instructions that are ready. Out-of-order execution results in less idle time and, hence, higher performance. However, it requires more complex hardware and puts significant pressure on the design and validation teams.
As hardware gets more complex, validating the design becomes extremely challenging as the possible cases that must be tested increase exponentially. Semidynamics had to validate a complex out-of-order core with a small team of verification engineers (small compared to the verification teams in big tech companies). Moved out of necessity, Semidynamics had to innovate in the verification methodology. First, a powerful random test generator based on a genetic algorithm was developed. The test generator was extremely efficient in finding bugs in the design. Second, Artificial Intelligence (AI) was also used to drive the test generator by using reinforcement learning techniques, resulting in higher coverage, i.e. making sure all the cases were covered and tested.
On the other hand, Semidynamics decided to build its own VPU in 2021. The VPU had to be compliant with the recently released RISC-V Vector Extension 1.0 [7]. Furthermore, it was designed to be easily scalable and configurable, so customers could choose the vector length and the number of lanes, i.e. how many elements were processed at a time. Moreover, the VPU was developed to support different data types from 8 to 64 bits, including the bfloat16 format that is popular in machine learning.
After seven years since its creation, Semidynamics holds a rich portfolio of RISC-V Intellectual Properties (IPs) available for licensing. The IPs include Avispado (in-order core), Atrevido (out-of-order core) and the VPU. These IPs can be combined to build a multi-core RISC-V chip.
From startup to scaleup - Selling RISC-V IP
In 2022, Semidynamics attracted the attention of several private customers interested in licensing its RISC-V IPs. The first client was a US company that wanted to build a multi-core RISC-V chip for network processing. This company chose the Avispado core for its chip. Due to the small size and low power consumption of Avispado, many cores can be packed within a single chip, increasing throughput by processing multiple network packets simultaneously. Furthermore, Semidynamics customized the Avispado core adding new instructions tailored to networking, significantly improving performance for processing network protocols.
The second customer was another US-based company interested in developing a low-cost, low-core count device. Semidynamics proposed an array of eight Atrevido cores, each one including its own VPU. The customer is currently evaluating its multi-threaded vector RISC-V applications on the platform provided to reach 3 goals: (1) validate the correctness of the software, (2) analyse the performance and (3) optimize the code.
The third client was an Asian company that wanted to build a many-core RISC-V chip for data centres, specialized in data mining and AI. They wanted an out-of-order core and a big VPU with large vector size to achieve high performance, so Atrevido and Semidynamics’ VPU were the perfect choices to match the requirements. Furthermore, Semidynamics extended its Atrevido core and VPU with new instructions defined by the customer and tailored to machine learning applications.
Strengthening the EU ecosystem
On the other hand, Semidynamics has substantially increased its participation in European Projects in recent years. In 2022 the company joined the EUPilot project [6] to build an end-to-end RISC-V accelerator for High Performance Computing (HPC). Furthermore, the work on the EPI project continued. As part of EPI SGA2, i.e. the second stage of EPI, Semidynamics collaborates in the development of the EPAC 1.5 and the EPAC 2.0 chips.
In 2023, the company joined three additional projects. First, the RISER [9] project aims at developing the first all-European RISC-V cloud server infrastructure. Second, the OpenCUBE project [10] proposes to design a full-stack solution for European cloud computing. Finally, the VITAMIN-V [11] project will deploy a complete RISC-V hardware-software stack for cloud services. Semidynamics’ contributions in these projects are on the hardware side, providing efficient RISC-V cores with the required features for cloud computing.
As a result of the work in the aforementioned projects, a plethora of new features were added to the Avispado/Atrevido cores to extend compatibility with RISC-V. The cryptographic extension was implemented to improve the performance and safety of encryption/decryption algorithms. The bit manipulation extension was also included in Semidynamics’ cores, significantly improving the performance of applications that manipulate bit-fields, such as text processing or network protocol processing. Furthermore, more functionality in the area of Reliability, Availability and Serviceability (RAS) was added, including Error Correcting Codes (ECC) to detect and fix errors in the on-chip memories. Finally, the ongoing work on the hypervisor extension will boost the performance of virtualization applications on Avispado/Atrevido, allowing virtual machines to efficiently run on Semidynamics’ RISC-V cores.
To sum up, the development of RISC-V IP continues fueled by the demands of both private clients and European projects. The company is growing to accomplish its ambitious goals. Semidynamics started with a small team of eight engineers in 2017, but by June 2023 it will have nearly 50 employees with a plan to grow to 100 people by the end of the year.
Semidynamics' Strengths
In Semidynamics we strongly believe that our main asset are our employees. We are proud of having a great and diverse team with ample experience in the semiconductors industry. Founder and CEO Roger Espasa worked on top semiconductor companies for over 30 years, including DEC/Compaq, Intel and Broadcom. Several team members worked with Roger at Intel for over 15 years, whereas other members worked at Imagination Technologies and NVIDIA. To drive innovation, the company also includes experienced researchers coming from Intel Labs and the Universitat Politècnica de Catalunya (UPC). Last but not least, Semidynamics’ team also has its share of young but well prepared and very sharp members that excel at RTL design and verification.
In Semidynamics we are also proud of our products. Our RISC-V cores are fully configurable and fully customizable. Some of our RISC-V IP and novel technologies include the following:
- Avispado, a small and energy-efficient in-order RISC-V core
- Atrevido, a high-performance out-of-order RISC-V core
- A fully configurable VPU compliant with the RISC-V Vector Extension 1.0, ideal for AI and machine learning
- Gazillion MissesTM, included in both Avispado/Atrevido to boost data movement, making our cores the fastest for moving data around
- Ample compatibility with RISC-V extensions for cryptography, bit-manipulation and virtualization
Finally, we also offer extensive customization of our RISC-V products to fit your needs. We can add new instructions that will be beneficial for your software. We can remove components that you do not need to save area, so you do not have to pay for things that you do not want in your silicon. We can strengthen the components that are key for your applications. At Semidynamics we have a very skilled team that combines veterans and young talents. Hence, if you plan to build a RISC-V chip, our team is here to help you and make sure you succeed.
References
[1] RISC-V: https://riscv.org/
[2] European Processor Initiative: https://www.european-processor-initiative.eu/project/epi/
[3] Vector Processor: https://en.wikipedia.org/wiki/Vector_processor
[4] Open Vector Interface: https://github.com/semidynamics/OpenVectorInterface
[5] EPAC Test Chip: https://www.european-processor-initiative.eu/epi-epac1-0-risc-v-test-chip-samples-delivered/
[6] The EUPilot: https://eupilot.eu/
[7] RISC-V Vector Extension 1.0: https://github.com/riscv/riscv-v-spec/releases/tag/v1.0
[8] FPGA: https://en.wikipedia.org/wiki/Field-programmable_gate_array
[9] RISER: https://www.riser-project.eu/
[10] OpenCUBE: https://cordis.europa.eu/project/id/101092984
[11] VITAMIN-V: https://www.vitamin-v.eu/