Our revolutionary new AI architecture directly interconnects our blocks so zero latency. The data is in the vector registers and can be used by the vector unit or the tensor unit with each part simply waiting in turn to access the same location as needed.

Everyone else requires considerable data movement between different functional blocks via a bus which creates significant performance bottlenecks and latency. Plus, Gazzillion ensures huge amounts of data can be handled from anywhere in the memory without suffering from cache misses.

Instead of IP blocks and tool chains from different vendors to make a current AI solution that makes programming the three totally different software stacks very complicated, our innovative All-In-One AI processor element uses the RISC-V instruction set and a single development environment giving a single software stack to reduce development costs and time. The All-In-One AI IP is thus a big step forward in programmer friendliness as it is designed to simplify programmability so any developer can leverage its full potential.

The RISC-V core inside our All-In-One AI IP provides the ‘intelligence’ to adapt to today’s most complex AI algorithms and even to algorithms that have not been invented yet! Instead of using fixed-function accelerators, it is built out of many fully programmable IP elements. Therefore, it is much more resilient and adaptable to future improvements in AI/ML algorithms. This guarantees it will stay relevant over time, being able to adapt to new models and deep learning architectures via software updates.

The Tensor Unit provides the sheer matrix multiply capability for convolutions, while the Vector unit, with its fully general programmability, can tackle any of today’s activation layers as well as anything the AI software community can dream of in the future.

By using our new Configurator tool, you can create the appropriate balance of Tensor and Vector units with RISC-V control capabilities in the processing element to optimise performance and PPA. Having an All-In-One processing element that is simple and yet repeatable solves the scalability problem so you can scale from a 1/4 TOPS to hundreds of TOPS by using as many processing elements as needed on the chip.

This fully customisable solution sets a new standard for next generation, ultra-powerful AI chips giving you the versatility to create unique solutions to precisely meet your application needs rather than using standard off-the-shelf chips.

And, of course, our Open Core Surgery means that you can have special instructions inserted into the core for even more differentiation!