The Open Vector Interface
In case you would like to develop your own Vector Unit,
Semidynamics can help you!
Semidynamics can help you!
The interface has been defined with a clear division of labor in mind
The interface has been defined with a clear
division of labor in mind
division of labor in mind
On one side of the OVI, the Atrevido/Avispado cores implement all the logic to support vector load and vector store operations (and all their numerous variants). All the connection to memory, via AXI or CHI, is managed by the Semidynamics core.
On the other side of the OVI, you implement the arithmetic part of the Vector Unit to your exact needs and desired PPA.
In between both pieces, OVI defines how data is sent back and forth between both parties and how instructions are communicated from the core side to your Vector Unit.
Logic
The Atrevido or Avispado core
implement the following logic for you
implement the following logic for you
- Vector Loads
- Vector Strided Loads
- Vector Indexed Loads
- Vector Segmented Loads
- Vector Stores
- Vector-to-Scalar Memory Coherency
- PMA
- Vector Strided Stores
- Vector Indexes Store
- Vector Segmented Store
- Scalar-to-Vector Memory Coherency
- Optional PMP if required
- Virtual Memory (SV48 or SV39 MMU of your choice)1
- Decoding of vector arithmetic instructions sent to your Vector Unit2
You will be responsible for implementing
- The subordinate side of the OVI interface.
- The arithmetic units inside the Vector Unit.
- The vector logic for issuing vector instructions to your vector arithmetic units.