Advanced multi-core RISC-V chips can now easily be created for applications such as AI and ML

Barcelona, Spain – 3 October, 2023. There is an ever-increasing demand for more powerful chip designs for advanced applications, such as AI and ML, that require many cores on one chip. To facilitate this, Semidynamics and SignatureIP have partnered to integrate their respective IPs to provide a fully-tested RISC-V, multi-core environment and CHI interconnect for the development of state-of-the-art chip designs. 

Semidynamics’ CEO and founder, Roger Espasa, said, “Working closely together with other members of the RISC-V community is one of the driving forces of RISC-V’s rapidly growing success. There is a natural synergy between the two companies that has resulted in a solution that enables cutting edge, multi-cores chips to be created. SignatureIP’s C-NoC CHI interconnect solution makes it very straightforward to lay out the Network on Chip (NoC) for multiple cores on a chip using our mature, proven technologies which minimizes risks and accelerates time to market.”

SignatureIP’s Coherent NoC is architected for performance and scalability across chiplets. It supports a transport layer for chiplet communication. The C-NoC IP is a directory-based architecture with distributed home-node support and optional system level caches for high performance. SignatureIP’s state-of-the-art inoculator.ai tool supports automation to generate a physically-aware NoC for a system. Combined with the automation tool and a simple licensing model, the process of evaluation, licensing, and implementation becomes an easy task for SignatureIP’s customers. 

Kishore Mishra, SignatureIP’s CTO, added, “Semidynamics revolutionized the 64-bit RISC-V processor with cores that are fully customizable using its ‘Open Core Surgery’ approach. This goes deep into the core and is not the tweakable approach typically found in IPs. Combining our technologies now enables multi-core chip designs to be created on this fully coherent RISC-V/CHI platform and then prototyping on an FPGA to demonstrate the integrated performance. We have fully tested them together to ensure compatibility and minimization of verification time”. 

Barcelona, Spain – 20 September, 2023. Semidynamics is a finalist in this year’s Elektra Awards in the category of Semiconductor Product of the Year (Digital). This is for the company’s new Atrevido 64-bit RISC-V IP processor core. The core is unique in that it is fully customisable to precisely meet the customer’s specifications. This includes Semidynamics ability to open up the core to insert a customer’s specific instructions which it calls Open Core Surgery™.

Semidynamics’ CEO and founder, Roger Espasa, said, “We have been in stealth mode until this year, perfecting our cores and supporting technologies. The Vector Unit can process unprecedented amounts of data bits and, to fetch all this data from memory, we have our Gazzillion™ technology that can handle up to 128 simultaneous requests for data and track them back to the correct place in whatever order they are returned. Together our technologies take RISC-V to a whole new level with the fastest handling of big data currently available that will open up opportunities in many application areas of High-Performance Computing such as video processing, AI and ML. We are delighted and honoured that our innovative technology has been recognised as a finalist by the judges of these prestigious international Awards.”

Details of the awards can be found at Elektra Awards 2023 and the winners will be announced at the awards ceremony on Wednesday 29 November at the Grosvenor House Hotel, Park Lane, London.

Launches at RISC-V Summit China on booth B2,  August 23-25 2023

Barcelona, Spain – 20 July, 2023. Semidynamics, the only provider of fully customisable RISC-V processor IP, has launched the next member of its Atrevido family of 64-bit cores. The Atrevido 423 has a wider, 4-way pipeline, allowing for the decoding and retirement of up to two times more instructions than its recently launched, 2-way, 223 core. It is also coupled with more functional units, which significantly increases the IPC (instructions-per-cycle).
 
Roger Espasa, Semidynamics’ CEO, said, “The Atrevido 423 is particularly well suited for applications that require massive amounts of data. It shines when the data required cannot fit in memory hierarchy levels that are closer to the core (such as L1, L2 or even L3) by tolerating very large latencies without compromising on throughput thanks to our Gazzillion™ misses technology. This can handle up to 128 simultaneous requests for data and track them back to the correct place in whatever order they are returned. Gazzillion™ allows the core to access memory hierarchy levels far away from the core without an impact in bandwidth or throughput. Effectively, Gazzillion™ technology removes the latency issues that can occur when using CXL technology to enable far away memory to be accessed at the supercharged rates that it was designed to deliver. This makes Atrevido very well positioned to handle AI and HPC workloads, which typically need to rapidly access very large amounts of data from main memory.”

Atrevido can be configured as a coherent core with a CHI NoC or as a simpler, incoherent core connected via an AXI interface. Furthermore, with an improved TLB and MMU and support for SV39/48/57, the core is well suited for running applications with large memory footprints using Linux. The Out-Of-Order core comes with a large menu of RISC-V extensions that can be added. Most notably, it can be configured with the in-house Vector Unit, which fully supports the latest RISC-V vector spec. Other important extensions are bit manipulation, crypto, single-precision FP, double-precision FP and half-precision FP, and bfloat16. Customers can also optionally choose to protect the Data cache with ECC and the Instruction cache with parity, if required for their target markets. Furthermore, the Atrevido core is fully compliant with the latest RVA22 RISC-V profile. The cores are process agnostic with versions already being supplied down to 5nm.
 
Roger Espasa added, “Semidynamics has the fastest cores on the market for moving large amounts of data with a cache line per clock at high frequencies even when the data does not fit in the cache. And this can be done at frequencies up to 2.4 GHz on the right node. The rest of the market averages about a cache line every many, many cycles, that is nowhere near Semidynamics’ one every cycle.”
 
Crypto-Enabled
The scalar crypto extension implemented follows the latest specification (Zks and Zk) and provides high performance encryption for algorithms such as SHA2-256, SHA2-512, ShangMi 3, ShangMi 4, AES-128, AES-192, and AES-256. The Atrevido 423 constant-time implementation provides security against side-channel attacks while still delivering a high-performance crypto solution. 
 
Open Core Surgery for full customisation
“Customers for these kinds of state-of-the-art cores want to have unique solutions with their own special secret sauce built,” explained Espasa. “We are unique in offering Open Core Surgery™ where we open up the core to insert custom instructions within it. This is unique as other companies’ cores are only configurable from a set of predetermined options. This completely protects the customer’s ASIC from copying and protects its multi-million-dollar investment in the new ASIC. It also means that it is optimised for Power, Performance and Area with no unnecessary overheads or compromises.”
 
Semidynamics can implement a customer’s ‘secret sauce’ features into the RTL in a matter of weeks, which is something that no-one else offers. Semidynamics also enables customers to achieve a fast time to market for their customised core as a first drop can be delivered that will run on an FPGA. This enables the customer to check functionality and run software on it while Semidynamics does the core verification. By doing these actions in parallel, the product can be brought to market faster and with reduced risk.
 
Vector Unit
Key to this is Semidynamics’ Vector Unit that is the largest, fully customisable Vector Unit in the RISC-V market, delivering up to 2048b of computation per cycle for unprecedented data handling. The Vector Unit is composed of several 'vector cores', roughly equivalent to a GPU core, that perform multiple calculations in parallel. Each vector core has arithmetic units capable of performing addition, subtraction, fused multiply-add, division, square root, and logic operations. Semidynamics' vector core can be tailored to support different data types: FP64, FP32, FP16, BF16, INT64, INT32, INT16 or INT8, depending on the customer’s target application domain. The largest data type size in bits defines the vector core width or ELEN. Customers then select the number of vector cores to be implemented within the Vector Unit, either 4, 8, 16 or 32 cores, catering for a very wide range of power-performance-area trade-off options. Once these choices are made, the total Vector Unit data path width or DLEN is ELEN x number of vector cores. Semidynamics supports DLEN configurations from 128b to 2048b.
 
Uniquely, Semidynamics offers a second key choice in the Vector Unit: the number of bits of each vector register (known as VLEN) can also be tailored to customer’s needs. While most other vendors assume that VLEN is equal to DLEN (i.e., 1X ratio), Semidynamics offers 2X, 4X and 8X ratios. When the VLEN is larger than the DLEN, a vector operation uses multiple cycles to execute. For example, when VLEN=2048 and DLEN=512, each vector arithmetic operation will take 4 clocks to execute. This is a great feature for tolerating large memory latencies and for reducing power. This unleashes the ability for the Vector Unit to process unprecedented amounts of data bits which it is being continuously fed by Gazzillion™ .
 

Launches at RISC-V Summit Europe 2023 (booth 6)

Barcelona, Spain – 1 June, 2023. Semidynamics has announced its new, entirely customisable Vector Unit to go with its innovative range of fully customisable 64-bit RISC-V cores. The Vector Unit is totally compliant with the RISC-V Vector Specification 1.0 with many, additional, customisable features to provide enhanced data handling capabilities. Together they set a new standard for data handling both in terms of unprecedented speed and volume.

Semidynamics’ CEO and founder, Roger Espasa, explained, “Our recently announced Atrevido™ core is unique in that we can do ‘Open Core Surgery’ on it. This means that, unlike other vendors’ cores that are just configurable from a set of options, we actually open up the core and change the inner workings to add features or special instructions to create a totally bespoke solution. We have taken the same approach with our new Vector Unit to perfectly complement the ability of our cores to rapidly process massive amounts of data.”   

A Vector Unit is composed of several 'vector cores', roughly equivalent to a GPU core, that perform multiple calculations in parallel. Each vector core has arithmetic units capable of performing addition, subtraction, fused multiply-add, division, square root, and logic operations. Semidynamics' vector core can be tailored to support different data types: FP64, FP32, FP16, BF16, INT64, INT32, INT16 or INT8, depending on the customer’s target application domain. The largest data type size in bits defines the vector core width or ELEN. Customers then select the number of vector cores to be implemented within the Vector Unit, either 4, 8, 16 or 32 cores, catering for a very wide range of power-performance-area trade-off options. Once these choices are made, the total Vector Unit data path width or DLEN is ELEN x number of vector cores. Semidynamics supports DLEN configurations from 128b to 2048b.

Semidynamics has equipped its Vector Unit with a high-performance, cross-vector-core network that provides all-to-all connectivity between the vector cores at high bandwidth, even for the very large, 32-vector core option. The cross-vector-core unit is used for specific instructions in the RISC-V standard that shuffle data between the different vector cores, such as vrgather, vslide, etc.

Uniquely, Semidynamics offers a second key choice in the Vector Unit: the number of bits of each vector register (known as VLEN) can also be tailored to customer’s needs. While most other vendors assume that VLEN is equal to DLEN (i.e., 1X ratio), Semidynamics offers 2X, 4X and 8X ratios. When the VLEN is larger than the DLEN, a vector operation uses multiple cycles to execute. For example, when VLEN=2048 and DLEN=512, each vector arithmetic operation will take 4 clocks to execute. This is a great feature for tolerating large memory latencies and for reducing power.

“This unleashes the ability for the Vector Unit to process unprecedented amounts of data bits,” added Espasa. “And to fetch all this data from memory, we have our Gazzillion™ technology that can handle up to 128 simultaneous requests for data and track them back to the correct place in whatever order they are returned. Together our technologies take RISC-V to a whole new level with the fastest handling of big data currently available that will open up opportunities in many application areas of High-Performance Computing such as video processing, AI and ML.”

The new Vector Unit is Out-Of-Order and pairs with Semidynamics’ Out-Of-Order Atrevido core and upcoming In-Order cores. If required, Semidynamics can do Open Core Surgery™ on cores and Vector Units to provide special interfaces and protocols to a customer’s proprietary IP block.
 

Ideal for handling large amounts of data
 
Barcelona, Spain – 17 April, 2023. Semidynamics, the only provider of fully configurable RISC-V processor IP, has announced the world’s first, fully customisable, 64-bit RISC-V family of cores that are ideal for handling large amounts of data for applications such as AI, Machine Learning (ML) and High-Performance Computing (HPC). The cores are process agnostic with versions already being supplied down to 5nm. 

Semidynamics CEO and founder, Roger Espasa, explained, “Until now, RISC-V processor cores had configurations that were fixed by the vendor or had a very limited number of configurable options such as cache size, address bus size, interfaces and a few other control parameters. Our new IP cores enable the customer to have total control over the configuration, be it new instructions, separate address spaces, new memory accessing capabilities, etc. This means that we can precisely tailor a core to meet each project’s needs so there are no unrequired overheads or compromises. Even more importantly, we can implement a customer’s ‘secret sauce’ features into the RTL in a matter of weeks, which is something that no-one else offers. Every designer using RISC-V wants to have the perfect set of Power, Performance and Area along with unique differentiating features and now, for the first time, they can have just that from us.”
 
The first in the family, which is available for licensing now, is the Atrevido™ core. This has Out-of-Order scheduling that is combined with the company’s proprietary Gazzillion™technology so that it can handle highly sparse data with long latencies and with high bandwidth memory systems that are typical of current machine learning applications. Effectively, Gazzillion technology removes the latency issues that can occur when using CXL technology to enable far away memory to be accessed at the supercharged rates that it was designed to deliver.
 
The Gazzillion technology is specifically designed for Recommendation Systems that are a key part of Data Centre Machine Learning. By supporting over a hundred misses per core, an SoC can be designed that delivers highly sparse data to the compute engines without a large silicon investment. In addition, the core can be configured from 2-way up to 4-way to help accelerate the not-so-parallel portions of Recommendation Systems.
 
For the most demanding workloads, such as HPC, the Atrevido core supports large memory capacities with its 64-bit native data path and 48-bit physical address paths. Espasa added, “We have the fastest cores on the market for moving large amounts of data with a cache line per clock at high frequencies even when the data does not fit in the cache. And we can do that at frequencies up to 2.4 GHz on the right node. The rest of the market averages about a cache line every many, many cycles, that is nowhere near our one every cycle. So, if the application streams a lot of data and/or the application touches very large data that does not fit in cache, we have the best RISC-V cores on the market for your use case.”
 
With its complete MMU support, Atrevido is also Linux-ready including supporting cache-coherent, multi-processing environments from two and up to hundreds of cores. It is vector ready, supporting both the RISC-V Vector Specification 1.0 as well as the upcoming Semidynamics Open Vector Interface. Vector instructions densely encode large numbers of computations to reduce the energy used by each operation. Vector Gather instructions support sparse tensor weights efficiently to help with machine learning workloads.
 
He concluded, “We have been in stealth mode while we created the core architecture that the RISC-V community really wants – one with full customisability, not just a few tweakable settings. No-one else has such a complex RISC-V core that can be totally configured to perfectly meet the specific needs of each project rather than having to use an off-the-shelf core and compromise.”
 

The test chip contains four vector processing micro-tiles (VPU) composed of an Avispado RISC-V core designed by SemiDynamics and a vector processing unit designed by Barcelona Supercomputing Center and the University of Zagreb. Each tile also contains a Home Node and L2 cache, designed respectively by Chalmers and FORTH, that provide a coherent view of the memory subsystem. The tiles are connected by a very high-speed network on chip and SERDES technology from EXTOLL.

EPAC combines several accelerator technologies specialized for different application areas. The test chip contains, among other features, four vector processing micro-tiles (VPU) composed of an Avispado RISC-V core designed by SemiDynamics and a vector processing unit designed by Barcelona Supercomputing Center and the University of Zagreb.

SemiDynamics contributed to their product with the overall architecture, the vector instruction set, the tensor extensions and the minion RTL implementation. Looking forward to seeing the product coming out soon!