RISC-V as an Instruction Set Architecture (ISA) has grown quickly in commercial importance and relevance since its release to the open community in 2015, attracting many IP vendors that now provide a variety of RTL cores. Roger Espasa, CEO and Founder of Semidynamics, has presented at RISC-V events on how their IP is customized for compute challenges that require high bandwidth and high performance cores with vector units. 

Neil Tyler talks to the CEO and founder of Semidynamics and looks at the core architecture they have developed for the RISC-V community.

Semidynamics, currently the only provider of fully customisable RISC-V processor IP, has launched the next member of its Atrevido family of 64-bit cores.

Semidynamics, the only provider of fully customisable RISC-V processor IP, has launched the next member of its Atrevido family of 64-bit cores. The Atrevido 423 has a wider, 4-way pipeline, allowing for the decoding and retirement of up to two times more instructions than its recently launched, 2-way, 223 core. It is also coupled with more functional units, which significantly increases the IPC (instructions-per-cycle).

Semidynamics, provider of the only fully customizable RISC-V processor IP, unveils the next member of the Atrevido family of 64-bit cores. The Atrevido 423 has a wider 4-way pipeline, allowing up to twice as many instructions to be decoded and retired as the recently introduced 2-way 223 core. It is also combined with more functional units, which greatly increases the IPC (instructions per cycle).

Semidynamics has launched the next member of its Atrevido family of 64-bit cores. The Atrevido 423 has a wider, 4-way pipeline, allowing for the decoding and retirement of up to two times more instructions than its recently launched, 2-way, 223 core. It is also said to be coupled with more functional units, which significantly increases the IPC (instructions-per-cycle).

Soooo… you’ve decided you’re going to create a system-on-chip (SoC) device of such awesomeness that it will leave your competitors gnashing their teeth and rending their garb. You’ve also decided to base this on a RISC-V processor. What you want is the biggest, baddest RISC-V processor going. Furthermore, you want this processor to be customized to allow you to take full advantage of your own “secret sauce” IP. Who ya gonna call?

The Atrevido 423 RISC-V core has a wide 4-way pipeline for decoding and retiring twice as many instructions as the previous 2-way 223 core. It is also coupled with more functional units, which significantly increases the instructions-per-cycle (IPC) throughput.

Semidynamics, the only provider of fully customisable RISC-V processor IP, has launched the next member of its Atrevido family of 64-bit cores. The Atrevido 423 has a wider, 4-way pipeline, allowing for the decoding and retirement of up to two times more instructions than its recently launched, 2-way, 223 core. It is also coupled with more functional units, which significantly increases the IPC (instructions-per-cycle).

Semidynamics, provider of the only fully customizable RISC-V processor IP, launched the next member of the Atrevido family of 64-bit cores. The Atrevido 423 has a wider 4-way pipeline, allowing up to twice as many instructions to be decoded and retired as the recently introduced 2-way 223 core. It is also combined with more functional units, greatly increasing the IPC (instructions per cycle).

The exclusive provider of fully customizable RISC-V processor IP, Semidynamics, has launched the next member of the Atrevido series 64-bit cores. Atrevido 423 features a wider 4-stage pipeline, allowing decoding and retiring of instructions twice as high as the recently launched 2-stage 223 core. It also integrates more functional units, significantly increasing the IPC (Instructions Per Cycle).

完全可定制的RISC-V处理器IP的提供商Semidynamics推出了Atrevido系列64位内核的下一个成员。Atrevido 423具有更宽的4路管道，允许解码和退役的指令最高是最近推出的2路223内核的两倍。它还与更多功能单元结合，大幅增加了IPC（每周期指令数）。

Calista Redmond, CEO of RISC-V International, joins Roger Espasa, Founder and CEO of Semidynamics, to discuss their new vector unit, making processors go fast in HPC and AI applications, and plans for the future.

The RISC-V Instruction Set Architecture is perfectly suitable for fine tuning the performance depending on the application. In this interview Roger Espasa, CEO and Founder at Semidynamics Technology Services explains how cores and vectorizing can be used to build ‘Tailor Made’ client specific silicon.

Spanish start-up Semidynamics announced the launch of the RISC-V Vector Unit (Vector Unit) that can be used for highly parallel processors such as artificial intelligence (AI), high-performance computing (HPC) and even graphics. This is the development of the RISC-V ecosystem

Capable of delivering up to 2048b of computation per cycle, the new Vector Unit from Semidynamics is a completely customisable platform that accompanies the company’s 64-bit RISC-V core offering.

New innovations from the RISC-V Summit Europe are poised to streamline the design process for open-source processors.
As we wrap up the week of RISC-V Summit Europe, here we'll review how companies this week used the event as a platform to reveal their latest innovations leveraging the open instruction set architecture (ISA). These developments encompass both hardware and software, making them important to designers in a breadth of fields.

The RISC-V Summit Europe brought together developers, architects, technical decision and policy makers from across European RISC-V ecosystem for the first time in the region this week.
Attendees from academia, research, SMEs, industry and open source communities  gathered in Barcelona to discuss the technologies and research shaping the future of RISC-V computing, in applications such as Automotive, High Performance Computing, AI, and Security.

La Comisión Europea ha dado este jueves luz verde al mayor proyecto europeo de interés común (IPCEI) por el que 14 países de la Unión Europea, incluido España, podrán destinar hasta 8.100 millones de euros en ayudas públicas a iniciativas para el desarrollo de microelectrónica y tecnologías de la comunicación.

Configurable high-bandwidth RISC-V cores with vector units can be made to directly address challenging applications like machine learning, AI, and other cutting-edge spaces.

Semidynamics is a European provider of RISC-V based solutions, specializing in the development of high performance cores and high bandwidth with vector drives targeting applications of machine learning and artificial intelligence. The company has just announced one of the first RISC-V vector drives of the sector. A unit of vector processing is designed to perform parallel operations on data vectors, allowing high performance for a wide range of computationally intensive applications. Think of real-time image processing, the machine learningscientific simulation and much more.

Semidynamics has introduced one of the industry's first RISC-V vector units that could be used for highly parallel processors, such as those used for artificial intelligence (AI), high-performance computing (HPC), and even graphics processing if equipped with appropriate special-purpose IP. The announcement marks an important milestone in the development of the RISC-V ecosystem. 

Semidynamics has introduced one of the industry's first RISC-V vector units available for use in highly parallel processors such as those used in artificial intelligence (AI), high performance computing (HPC) and even graphics (if equipped with the appropriate dedicated processor ) destination IP. This announcement marks an important milestone in the development of the RISC-V ecosystem.

RISC-V vector unit: what it is and why the one from Semidynamics can revolutionize the market
After having accumulated an abysmal gap against the tech giants with headquarters in other continents, the European Union wishes to return to the leading role in the development and production of microprocessors.

Semidynamics delivers a fully customizable Vector Unit integrated into 64-bit RISC-V cores able to run up to 2048b of computation per cycle for large data transmissions. The unit follows the RISC-V Vector Specification 1.0 and adds many features to fit user requirements.

At up to 2048bits of computation per cycle, Semidynamics says that its customisable Vector Unit is the largest available in the RISC-V market today, offering “unprecedented data handling”.
At the RISC-V Summit Europe 2023 (05 to 09 June) in Barcelona, Semidynamics highlights the customisable vector unit to accompany the company’s customisable 64-bit RISC-V cores. The Vector Unit complies with the RISC-V Vector Specification 1.0 and has additional, customisable features to enhance data handling capabilities. Semidynamics claimed that together they “set a new standard for data handling both in terms of unprecedented speed and volume”.

A semi-dynamic tem introduzido uma das primarsa unidades vetoriais RISC-V do Setor que pode ser usada para procesadores highly paralelos, Como os usados para intelligencia artificial (IA), computação de alto perfomance (HPC) e even mesmo processing graphic, se equipado com IP appropriate para fins especiales . O announcement marca um marco importante no desenvolvimento do ecossistema RISC-V.

The Spanish company Semidynamics shows that the open RISC-V architecture is rapidly catching up with other processor architectures that have been on the market longer. The company's latest vector unit brings a computing capacity of up to 2048 bits per clock cycle.

La ISA RISC-V está de moda. Este fin de semana hemos visto cómo grandes compañías se suman a crear chips con ella, y no debería ser algo novedoso como tal, pero como se suele decir, la moda es la moda. Otras compañías con no tanto bombo y platillo llevan tiempo trabajando con esta ISA, como Semidynamics, que ha presentado su nueva Unidad Vectorial, la más grande y completa del mercado con la friolera de 2.048 bits.

Semidynamics has equipped its Vector Unit with a high-performance, cross-vector-core network that provides all-to-all connectivity between the vector cores at high bandwidth, even for the very large, 32-vector core option. The cross-vector-core unit is used for specific instructions in the RISC-V standard that shuffle data between the different vector cores, such as vrgather, vslide, etc.

Vector unit are composed of several vector cores that perform multiple calculations in parallel.
In this case, Semidynamics’ vector core can be tailored to support FP64, FP32, FP16, BF16, INT64, INT32, INT16 or INT8 data types depending on requirements – the longest word-length implemented defines the vector core width (‘ELEN’).

Vector unit are composed of several vector cores that perform multiple calculations in parallel.
In this case, Semidynamics’ vector core can be tailored to support FP64, FP32, FP16, BF16, INT64, INT32, INT16 or INT8 data types depending on requirements – the longest word-length implemented defines the vector core width (‘ELEN’).

Semidynamics has announced its new, entirely customisable Vector Unit to go with its innovative range of fully customisable 64-bit RISC-V cores. The Vector Unit is totally compliant with the RISC-V Vector Specification 1.0 with many, additional, customisable features to provide enhanced data handling capabilities. Together they set a new standard for data handling both in terms of unprecedented speed and volume.

Arm mobile platform; making software for RISC-V; GPU AI supercomputer; scaling up batteries.

Semidynamics has released a customizable vector unit to accompany the 64bit RISC-V processor cores the company has designed for high-performance computing systems.

Semidynamics has announced its new, fully customizable vector unit to accompany its innovative family of fully customizable 64-bit RISC-V cores. The vector unit is fully compliant with the RISC-V vector specification 1.0, with many additional, customizable features to provide enhanced data processing capabilities. Together, they set new standards for data processing at unprecedented speed and volume.

Semidynamics has announced its new, entirely customisable Vector Unit to go with its innovative range of fully customisable 64-bit RISC-V cores. The Vector Unit is totally compliant with the RISC-V Vector Specification 1.0 with many, additional, customisable features to provide enhanced data handling capabilities. Together they set a new standard for data handling both in terms of unprecedented speed and volume.

After having accumulated an abysmal gap against the tech giants with headquarters in other continents, the European Union wishes to return to the leading role in the development and production of microprocessors. On the one hand, the Chips Act aims to bring at least 20% of global semiconductor production to Europe: from this point of view, Intel itself has decided to strengthen its presence in the Old Conti....

Semidynamics has announced its new, fully customizable vector unit to accompany its innovative family of fully customizable 64-bit RISC-V cores. The vector unit is fully compliant with the RISC-V vector specification 1.0, with many additional, customizable features to provide enhanced data processing capabilities. Together, they set new standards for data processing at unprecedented speed and volume.

Semidynamics has announced a customisable vector unit for RISC-V processor cores, compliant with RISC-V vector specification 1.0.

Vector unit are composed of several vector cores that perform multiple calculations in parallel.

Semidynamics has announced its new, entirely customisable Vector Unit to go with its innovative range of fully customisable 64-bit RISC-V cores. The Vector Unit is totally compliant with the RISC-V Vector Specification 1.0 with many, additional, customisable features to provide enhanced data handling capabilities. Together they set a new standard for data handling both in terms of unprecedented speed and volume.

Semidynamics in Spain has developed a highly configurable out of order vector unit with a new architecture to boost performance of RISC-V processor designs, and is running a demonstration of Doom.
The Vector Unit pairs with Semidynamics’ 64bit Out-Of-Order RISC-V Atrevido core and upcoming In-Order cores. “We are launching the configurable core with the vector unit support,” Roger Esposa, CEO of SemiDynamics tells eeNews Europe.

Semidynamics offers fully customized RISC–V CPUs for clients requiring capabilities beyond what’s readily available. The ability to maintain many outstanding memory requests boosts performance for applications with poor data locality.

Roger Espasa, CEO of SemiDynamics, discusses the technology behind the company’s fully configurable 64-bit, RISC-V processor IP, the recent launch of the Atrevido core – the first in a fully customisable 64-bit RISC-V family of cores, focusing on demanding machine learning and AI applications.

Semidynamics announced a family of customizable 64-bit RISC-V IP cores optimized for handling large amounts of data in applications such as AI/ML and HPC.

Semidynamics has released the world’s first, fully customisable, 64-bit RISC-V family of cores that are excellent for handling large amounts of data for applications, including AI, ML and HPC. The cores are process agnostic, with versions currently supplied down to 5nm.

The Spanish startup Semidynamics has developed commercial 64-bit RISC-V IP cores that can be adapted to a target application in all parameters. The cores are not tied to specific manufacturing processes and target compute-intensive applications such as artificial intelligence and machine learning with high bandwidth and vector units.

Semidynamics, the only provider of fully configurable RISC-V processor IP, has announced the world’s first, fully customisable, 64-bit RISC-V family of cores that are ideal for handling large amounts of data for applications such as AI, Machine Learning (ML) and High-Performance Computing (HPC). The cores are process agnostic with versions already being supplied down to 5nm.

At its heart, the RISC-V movement centers around the idea of democratizing processor design. With an open-source instruction set architecture (ISA) and a plethora of resources available to anyone free of cost, RISC-V is meant to enable any company, regardless of resources, to design custom hardware.

Startup SemiDynamics has come out of stealth mode to introduce what it said is the first fully customizable, 64-bit RISC-V core family for handling large amounts of data for ML, AI, and HPC.

Semidynamics, the only provider of fully configurable RISC-V processor IP, announced the world's first fully customizable 64-bit RISC-V family of cores for artificial intelligence, machine learning (ML) and high-performance Ideal for processing large amounts of data in applications such as computing (HPC). These cores are process agnostic and are already available down to 5nm.

Crée en 2016 à Barcelone, le concepteur espagnol de semiconducteurs sans fabrication  Semidynamics a annoncé la première famille de cœurs RISC-V 64 bits entièrement personnalisable, idéale pour traiter les  traiter les grandes quantités de donnés des applications ce l’IA, de l’apprentissage automatique (ML) et du calcul à haute performance (HPC). Ces cœurs ne dépendent d’aucun processus et des versions jusqu’à 5 nm sont déjà disponibles.

Semidynamics released a one of a kind 64-bit RISC-V family of cores boosting the ability to transmit copious amounts of information for high-performance computing (HPC) and AI/ML. The cores are process agnostic and utilize Gazzillion technology that was developed for recommendation systems, a must for data center ML.

Barcelona-based Semidynamics has launched RISC-V processor IP that the company claims provides a great deal more customisability than other off-the-shelf cores on the market and which incorporates a novel memory unit that improves performance on the kinds of sparse data structures used in some machine-learning applications.

Semidynamics, the only provider of fully configurable RISC-V processor IP, has announced the world’s first, fully customisable, 64-bit RISC-V family of cores that are ideal for handling large amounts of data for applications such as AI, Machine Learning (ML) and High-Performance Computing (HPC). The cores are process agnostic with versions already being supplied down to 5nm.

Semidynamics, a well-known European RISC-V IP core supplier, announced the world's first fully customizable 64-bit RISC-V core series for artificial intelligence, machine learning (ML) and high-performance computing (HPC) ) provide an ideal choice for processing large amounts of data.

Semidynamics released a one of a kind 64-bit RISC-V family of cores boosting the ability to transmit copious amounts of information for high-performance computing (HPC) and AI/ML. The cores are process agnostic and utilize Gazzillion technology that was developed for recommendation systems, a must for data center ML.

Semidynamics has announced the first, fully customisable, 64-bit RISC-V family of cores that are ideal for handling large amounts of data for applications such as AI, Machine Learning (ML) and High-Performance Computing (HPC). The cores are process agnostic with versions already being supplied down to 5nm.

Semidynamics, a Barcelona-based provider of fully configurable RISC-V processor IP, has announced the world’s first, fully customisable, 64-bit RISC-V family of cores.

Semidynamics, fabricante de procesadores RISC-V completamente configurables con propiedad intelectual, anuncia el lanzamiento de la primera familia de núcleos RISC-V de 64 bits completamente personalizables.

Spanish startup SemiDynamics has developed fully configurable 64bit RISC-V processor IP for high performance chip designs in AI, Machine Learning (ML) and High-Performance Computing (HPC).

Semidynamics, the only provider of fully configurable RISC-V processor IP, has announced the world’s first, fully customisable, 64-bit RISC-V family of cores that are ideal for handling large amounts of data for applications such as AI, Machine Learning (ML) and High-Performance Computing (HPC). The cores are process agnostic with versions already being supplied down to 5nm.

Thirty semiconductor and electronics companies in Europe that felt they were in crisis formed an alliance called EPI (European Processor Initiative) to develop their own CPUs and GPUs.

The Catalan semiconductor industry is also under intense development. Europe is doing more to promote the semiconductor field due to the perception that the United States, Korea and Taiwan are leaving it behind in terms of semiconductor factories and design. To overcome this situation, European countries, including Spain, are receiving EU aid under the "EPI Project," which supports semiconductor design companies.

Additional €43bn in the pipeline, but it's still chickenfeed, say critics

Move comes ahead of draft law to turn continent into a center of semiconductor expertise

L'European Processor Initiative, qui réunit 28 acteurs technologiques de l'UE pour concevoir un processeur HPC européen, a présenté ses 1ers résultats. Outre les spécifications architecturales du Rhea, 1ère génération du processeur universel de l'EPI, le projet a réalisé une preuve de concept d'un accélérateur et un microcontrôleur haute performance embarqué pour les applications de la filière automobile.

Three years of R&D and design work to be tested with plans to build native ‘super in 2023

sureCore, the embedded memory specialist, has designed a power and area efficient, high performance, multi-port, embedded memory solution for Semidynamics’ new RISC-V-based, tensor processing chip.

Embedded memory IP specialist sureCore has developed a high performance, multi-port, embedded memory for a RISC-V-based, tensor processing chip.

Semidynamics is developing a high bandwidth, vector processing unit optimised for tensor processing aimed at AI applications.

sureCore, the Sheffield low-power memory IP house, has designed a power and area efficient, high performance, multi-port, embedded memory solution for Semidynamics’ new RISC-V-based, tensor processing chip.

The EPI was founded by the European Union with the aim of giving the different countries of the old continent total independence of high-performance computing technology from the United States and the great Asian powers. The geopolitical objective is nothing more than to have technological neutrality in a market that is moving to form two large blocks that in the end will end up giving companies to choose between one block or another.

European Processor Initiative (EPI) has been working on providing independence for the European Union in the high-performance computing (HPC) field, by developing custom RISC-V-based accelerators. Called the European Processor Accelerator (EPAC) chip, designed for high efficiency and high throughput computation, it has been successfully taped out and is being tested at EPI's labs.

The European Processor Initiative (EPI) a project with 28 partners from 10 European countries, with the goal of making EU achieve independence in HPC chip technologies and HPC infrastructure, is proud to announce that EPAC1.0 RISC-V Test Chip samples were delivered to EPI and initial tests of their operation were successful.

The European Processor Initiative (EPI) has run the successful first test of its RISC-V-based European Processor Accelerator (EPAC), touting it as the initial step towards homegrown supercomputing hardware.

In 2018, Europe launched the European Processor Initiative (EPI), which aims to increase the independence of the European supercomputing industry from foreign technology companies. Its core is the use of free and open source RISC-V instruction set architecture for the development and production of high-performance chips in Europe, providing the European Union with independence in the field of high-performance computing (HPC).

Ya tenemos un chip europeo que ha mostrado en pantalla el célebre "Hello World". Se trata de EPAC (European Processor ACcelerator), un chip con arquitectura RISC-V que ha pasado las primeras pruebas de validación y que está orientado a ser usado en el ámbito de la supercomputación.