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Description
We are hiring! Are you passionate about physical chip design and working through complex challenges? We need you. In this role, you will take full ownership of the implementation process—from RTL to GDSII—utilizing some of the industry's most advanced technology nodes. You will work with cutting-edge technology, collaborating closely with external IP providers, EDA vendors, and silicon/package vendors to deliver high-performance SoCs or SiPs for mass production.
What do we offer? Flexible work schedules, competitive pay, a highly collaborative learning environment, and opportunities for career growth. Come and join us in the beautiful city of Barcelona! Candies, coffee, and free Spanish lessons included! (Visa sponsorship available if required.)
Key Responsibilities
If you are ready to take on a senior role in one of the most exciting fields of chip design, apply now!
What do we offer? Flexible work schedules, competitive pay, a highly collaborative learning environment, and opportunities for career growth. Come and join us in the beautiful city of Barcelona! Candies, coffee, and free Spanish lessons included! (Visa sponsorship available if required.)
Key Responsibilities
- Working onphysical implementation process of high-complexity SoCs using advanced technology nodes.
- Collaborate with external IP providers, EDA vendors, and silicon/package vendors for smooth data exchange and communication.
- Actively participate in team meetings to provide technical guidance on physical design flow, design for test, and EDA tools and methods.
- Moderate design discussions and make decisions quickly and effectively.
- Ability to drive timing and physical design closure for assigned block(s)
If you are ready to take on a senior role in one of the most exciting fields of chip design, apply now!
Requirements
- Master’s or PhD degree in Computer Science, Microelectronics, or Physics.[
- Experience with Synopsys tool suite ( Fusion Compiler &/or ICC2 + Primetime ) tools
- [+] Proficiency in UPF is a plus
- [+] Experience handling chiplets or hierarchical partitions is a significant advantage
- Proven experience with multiple tapeouts of high-performance SoCs or SiPs for mass production, including reliability and yield optimization.
- Demonstrated ability to work in complex SoC or SiP projects
- Experience and ability to supervise and mentor junior engineers to achieve timing and physical verification closure goals