Event

Dec 6th, 2021 RISC-V Summit

Roger Espasa participated at the RISC-V Summit with the talk "Implementation of an Out-of-order RISC-V Vector Unit"

In this talk Roger Espasa described Semidynamics' vector unit implementing the RVV-010 specification and he focused on the challenges of supporting out-of-order execution for vector instructions. He covered the challenges of renaming vector registers in the presence of LMUL, SEW, narrowing & widening and the different flavors of masking in the RV vector ISA. He also provided an overview of the vector load/store pipeline.
The RISC-V Summit - December 6-8, 2021 in San Francisco, CA.
Implementation of an Out-of-order RISC-V Vector Unit
← Back to Events

AI

moves fast
Your infrastructure should too

Ready to accelerate?

Learn more