Cervell™ NPU

C32
Clustered IP to Scale Throughput

When one engine isn’t enough, Atrevido Cluster multiplies throughput under the same ISA and memory‑first design (CPU/Vector, optionally Tensor‑equipped instances)  

Key Benefits

Effortless Scale-out

Effortless Scale-out

Scale‑out without software rewrites

Balanced by design

Balanced by design

Compute kept busy by Gazillion™‑driven bandwidth across the fabric

Ready Today, Future-Proof

Ready Today, Future-Proof

Silicon‑ready today; aligned with future boards/chiplets

Architecture Highlights

Cluster Integration Reference

Cluster Integration Reference

Reference cluster topologies and coherency/NoC integration notes

Sustained Data Flow

Sustained Data Flow

Gazillion™ across the fabric to sustain data flow

Unified Programming Model

Unified Programming Model

Unified programming model across single and multi‑engine systems

Software Path

Same RISC‑V ISA
Same RISC‑V ISA from
single‑engine to multi‑engine deployments

Typical Deployments

Throughput‑focused inference

Inference pipeline optimized for maximum throughput across large datasets

Compact gateways

Batch analytics

Accelerating large, complex data analyses performed on scheduled, high-volume data sets

Compact gateways

Multi‑stream vision

Enabling simultaneous, low-latency data processing and inference across multiple data flows

Compact gateways

Find out more

Our IP is silicon-ready, and in silicon implementations. Speak to us about reference designs

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