ID: PCIe-2
Description
Are you passionate about microprocessor architecture and ready to take a crucial role in designing high-performance semiconductor solutions? Join our High-Speed IO Team as a PCIe Engineer!
You will be responsible for defining the architecture and leading the RTL implementation of PCIe solutions. A key focus will be ensuring optimal interaction between the PCIe subsystem and our cores, which utilize the AMBA-CHI protocol for coherency. Your expertise in PCIe integration and/or design will be essential to create the efficient, high-performance subsystems vital for modern semiconductor designs. You will collaborate closely with other highly skilled engineers across multiple teams.
What We Offer:
You will be responsible for defining the architecture and leading the RTL implementation of PCIe solutions. A key focus will be ensuring optimal interaction between the PCIe subsystem and our cores, which utilize the AMBA-CHI protocol for coherency. Your expertise in PCIe integration and/or design will be essential to create the efficient, high-performance subsystems vital for modern semiconductor designs. You will collaborate closely with other highly skilled engineers across multiple teams.
What We Offer:
- Competitive salary and opportunities for advancement.
- Flexible work schedules.
- A highly engaging learning environment.
- The chance to live and work in the beautiful city of Barcelona.
- Included perks: Free Spanish,Catalan and English lessons, health insurance, ticket restaurant, etc...
- Visa sponsorship is available if required for you and your direct family.
- 25 days of holidays per year + 2 extra fixed days.
- 1 day of WFH (trial) per week.
- Offices very close to the main train stations (Entença and Sants).
Requirements
- Industrial experience +4 years (Engineer) or +6 years (Lead Engineer).
- Proven experience of PCIe, in design or integration of PCIe solutions.
- Proven experience in design and/or integration of IPs in a SoC/ASIC environment.
- Experience in at least one of the following protocols: AXI, CHI, AHB.
- Proficiency in RTL design using Verilog or VHDL.
- Experience with basic block level testing.
- Master or PhD.
- Knowledge of C++ and/or scripting languages (Python, Perl, Bash, TCL).
- Knowledge of revision control methodology and tools (git, svn).
- Knowledge of coherency concepts and protocols.
- Experience in CXL.
- Experience in common tools used in digital design (Synthesis, Timing, CDC, Lint, etc…)
Apply for this seniority
ID: PCIe-3
Description
- Industrial experience +4 years (Engineer) or +6 years (Lead Engineer).
- Proven experience of PCIe, in design or integration of PCIe solutions.
- Proven experience in design and/or integration of IPs in a SoC/ASIC environment.
- Experience in at least one of the following protocols: AXI, CHI, AHB.
- Proficiency in RTL design using Verilog or VHDL.
- Experience with basic block level testing.
- Master or PhD.
- Knowledge of C++ and/or scripting languages (Python, Perl, Bash, TCL).
- Knowledge of revision control methodology and tools (git, svn).
- Knowledge of coherency concepts and protocols.
- Experience in CXL.
- Experience in common tools used in digital design (Synthesis, Timing, CDC, Lint, etc…)
Requirements
Are you passionate about microprocessor architecture and ready to take a crucial role in designing high-performance semiconductor solutions? Join our High-Speed IO Team as a PCIe Lead Engineer!
You will be responsible for defining the architecture and leading the RTL implementation of PCIe solutions. A key focus will be ensuring optimal interaction between the PCIe subsystem and our cores, which utilize the AMBA-CHI protocol for coherency. Your expertise in PCIe integration and/or design will be essential to create the efficient, high-performance subsystems vital for modern semiconductor designs. You will collaborate closely with other highly skilled engineers across multiple teams.
What We Offer:
You will be responsible for defining the architecture and leading the RTL implementation of PCIe solutions. A key focus will be ensuring optimal interaction between the PCIe subsystem and our cores, which utilize the AMBA-CHI protocol for coherency. Your expertise in PCIe integration and/or design will be essential to create the efficient, high-performance subsystems vital for modern semiconductor designs. You will collaborate closely with other highly skilled engineers across multiple teams.
What We Offer:
- Competitive salary and opportunities for advancement.
- Flexible work schedules.
- A highly engaging learning environment.
- The chance to live and work in the beautiful city of Barcelona.
- Included perks: Free Spanish,Catalan and English lessons, health insurance, ticket restaurant, etc...
- Visa sponsorship is available if required for you and your direct family.
- 25 days of holidays per year + 2 extra fixed days.
- 1 day of WFH (trial) per week.
- Offices very close to the main train stations (Entença and Sants).