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Roger Espasa will participate at the RISC-V Summit with the talk "Implementation of an Out-of-order RISC-V Vector Unit" "

October 26, 2021

In this talk Roger Espasa will describe Semidynamics' vector unit implementing the RVV-010 specification and he will focus on the challenges of supporting out-of-order execution for vector instructions. He will cover the challenges of renaming vector registers in the presence of LMUL, SEW, narrowing & widening and the different flavors of masking in the RV vector ISA. He will also provide an overview of the vector load/store pipeline. 
The RISC-V Summit will take place December 6-8, 2021 in San Francisco, CA.

We are proud to have participated in the release of the new EPAC1.0 RISC-V Test Chip with our Avispado RISC-V core

September 22, 2021

The test chip contains four vector processing micro-tiles (VPU) composed of an Avispado RISC-V core designed by SemiDynamics and a vector processing unit designed by Barcelona Supercomputing Center and the University of Zagreb. Each tile also contains a Home Node and L2 cache, designed respectively by Chalmers and FORTH, that provide a coherent view of the memory subsystem. The tiles are connected by a very high-speed network on chip and SERDES technology from EXTOLL.

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