We are proud to have participated in the release of the new EPAC1.0 RISC-V Test Chip with our Avispado RISC-V core
September 22, 2021
The test chip contains four vector processing micro-tiles (VPU) composed of an Avispado RISC-V core designed by SemiDynamics and a vector processing unit designed by Barcelona Supercomputing Center and the University of Zagreb. Each tile also contains a Home Node and L2 cache, designed respectively by Chalmers and FORTH, that provide a coherent view of the memory subsystem. The tiles are connected by a very high-speed network on chip and SERDES technology from EXTOLL.
Roger Espasa, participated in the RISC-V Forum: Vector and Machine Learning with the talk "OVI: The Open Vector Interface"
September 15, 2021
In this talk, Roger Espasa presented OVI, an open protocol to connect a RISC-V core with a loosely coupled vector unit compliant to the RISC-V vector specification. OVI has been used to connect the Avispado core from SemiDynamics to the Vitriuvius vector unit from the Barcelona Supercomputing Center. In this talk we covered the details of the protocol and explained how it can enable a quicker implementation of a RISC-V compliant vector unit with custom extensions.