Target Markets

Machine Learning

The Atrevido core with its out-of-order scheduling engine combined with our Gazzillion technology can deal with highly sparse data, with long memory latencies and with high bandwidth memory systems, typical of current machine learning applications.

Recommendation Systems

The Gazzillion technology is specifically designed for Recommendation Systems, a key part of DataCenter Machine Learning.

By supporting hundreds of misses per Atrevido, you can build an SoC that smoothly delivers highly sparse data to the compute engines without a large silicon investment.

Furthermore, the 2-way Out-of-Order core helps accelerating the not-so-parallel portions of Recommendation Systems.

Key-Value Stores

In-memory caching and key-value processing requires large numbers of outstanding transactions to your memory subsystem.

Our Gazzillion Misses™ technology is especially suited for these demands, allowing you to sustain full memory bandwidth with fewer processing cores.

Sparse Data / HPC

Gromacs? Sparse Matrices? PDEs? OMP? MPI? Multi-level parallelism? You name it!

HPC has to deal with large, multi-dimensional, sparse data and support heterogeneous parallelism at multiple levels.

Atrevido, with Out-of-order execution and Gazzillion Misses™ technology is the right match for the HPC domain, be it Embedded HPC, Edge or DataCenter level.

64-bit Core

Ready for the most demanding workloads, Atrevido supports large memory capacities with its 64-bit native data path.

With its complete MMU support, Atrevido is also Linux-ready, including multiprocessing.

Vector Ready

Atrevido supports the upcoming RISC-V Vector Specification 1.0 as well as SemiDynamics Open Vector Interface, giving you freedom of choice between your own custom vector unit and using Semidynamics offerings.

Vector Instructions densely encode lots of computations, thereby reducing energy per operation.

Vector Gather instructions support sparse tensor weights efficiently, helping machine learning workloads.

Multiprocessor Ready

Atrevido supports cache-coherent Multiprocessing environments. Its native CHI interface can be tailored down to ACE or AXI, depending on your needs.

Be it 2, 4, or hundreds of cores, Atrevido is ready for your next SOC.

Customizable 2-wide
out-of-order pipeline

Decodes 2 instructions/cycle Register Renaming Including V-regs Out-of-Order issue Out-of-Order completion Gazzillion Misses™ SV48 Direct hardware support for unaligned accesses Customizable I$ from 8KB to 32KB D$ from 8KB to 32KB Branch Predictor